• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.32-43
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• 2010

This paper presents deblocking filter for low-complexity video decoder. Baseline profile of the H.264/AVC used for mobile devices such as mobile phones has two times higher compression performance than the MPEG-4 Visual but it has a problem of serious complexity as using 1/4-pel interpolation filter, adaptive entropy model and deblocking filter. This paper presents low-complexity deblocking filter for decreasing complexity of decoder with preserving the coding efficiency of the H.264/AVC. In this paper, the proposed low-complexity deblocking filter decreased 49% of branch instruction than conventional approach as calculating value of BS by using the CBP. In addition, a range of filtering of strong filter applied in intra macroblock boundaries was limited to two pixels. According to the experimental results, the proposed low-complexity deblocking filter decreased -0.02% of the BDBitrate comparison with baseline profile of the H.264/AVC, decreased 42% of the complexity of deblocking filter, and decreased 8.96% of the complexity of decoder.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.2
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• pp.284-289
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• 2008

H.264/AVC among moving picture compression standard is the standard format for high compression rate and reliable video transimission. It generates blocking effects in video due to compressing video using block-based DCT and includes de-blocking filter to reduce blocking effect. Therefore, the filter makes the video over-smoothing and the quality of it is reduced. In this paper, we propose a improved de-blocking filter to solve the demerit. The proposed de-blocking filter redetermine the block boundary strength and apply the comer filtering to eliminate artifacts in low frequency domain. To evaluate the performance, we apply the proposed deblocking filter and exiting method to various video and evaluated the quality of image subjectively and objectively by analyzing the result. The simulation result shows the proposed method preserves the edge of video, reduces blocking effects and improves PSNR than the existing method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.64-70
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• 2008

The H.264 standard is widely used due to the high compression rate and quality. The deblocking filter of the H.264 standard improves the quality of images by eliminating blocking artifacts of pictures, and it requires a lot of computation. We propose a new hardware architecture for the deblocking filter with pipelined architecture, 1-D filters which support both horizontal and vertical filtering and efficient memory management. Four memory blocks are configured for the efficient storage and access of the current macroblock and adjacent referenced sub-macroblocks, and the pixel data from the motion compensation unit can be transferred without waiting during the computation cycles of the deblocking filter. The number of computation cycles and the hardware area are reduced using the proposed architecture, and the performance of the H.264 decoder is improved. We design the deblocking filter using Verilog-HDL and implement using an FPGA. The designed deblocking filter can be used for decoding HD quality images at 77 MHz.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.401-410
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• 2008

Multiview Video Coding contains a macroblock-based illumination compensation tool which can compensate the variations of illuminations according to view or temporal directions. Thanks to illumination compensation tool, the coding efficiency of Multiview Video Coding has been enhanced. However illumination compensation tool also generates additional subjective drawbacks of the blocking artifacts due to macroblock-based compensations of mean values. A deblocking filtering method for Multiview Video Coding which is the same as in H.264/AVC does not consider illumination difference between the illumination compensated blocks, thus it can not effectively eliminate the blocking artifacts. Therefore, this paper analyzes the phenomena of blocking artifacts caused by illumination compensation and proposes a method which can effectively eliminate the blocking artifacts with the minimum changes of the H.264 deblockding filtering method. In the simulation results, it can be easily found the blocking artifacts are clearly eliminated in the subjective comparisons, and the average bit-rate reduction is up to 1.44%.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.330-332
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• 2012

H.264/AVC를 비롯한 대부분의 동영상 압축 표준에 의해 부호화 및 복호화된 영상은 블록화 현상(blocking artifacts)이 생긴다. 이러한 화질 열화 현상은 블록 기반의 정수형 이산코사인 변환(Integer DCT)을 수행한 후 계수를 양자화 하기 때문에 발생한다. 이러한 블록화 현상을 줄이기 위해 H.264/AVC에서는 디블록킹 필터를 이용한다. 본 논문에서는 H.264/AVC의 디블록킹 필터의 복잡도를 감소시키면서 화질을 유지하는 알고리듬을 제안하고 실험을 통한 평가를 제시한다. 복잡도를 줄이기 위해 제안하는 알고리듬에서는 블록 경계강도(Bs) 결정 과정에서 한 화소 줄의 경계강도를 이용하여 네 화소 줄 모두에 적용한다. 실험결과 경계강도 결정의 계산량을 줄이면서 주관적, 객관적 화질 또한 향상되는 결과를 보였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2005.11a
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• pp.39-42
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• 2005

블록기반의 비디오 부호화 표준은 비디오 신호의 압축방식으로 가장 널리 쓰이는 구조이지만 무선 환경과 같은 저 비트율 응용에서는 양자화에 의한 고주파 성분의 손실로 인해 블록킹 현상 및 링잉 현상이 두드러져 화질열화의 주된 원인이 된다. 이러한 화질열화를 제거하기 위해서 디블록킹 필터와 디링잉 필터를 사용하지만, 영상에 따라 블륵 경계의 모서리 부분과 대각선 에지가 만나는 부분에서 나타나는 corner outlier 현상으로 인해 화질이 충분히 개선되지 못하는 경우가 발생한다. 본 논문에서는 저 비트율 비디오에서 에지의 방향과 그 에지를 포함하는 블록의 평탄한 정도를 이용하여 corner outlier 현상을 검출하고, 이를 제거할 수 있는 비선형 필터를 제안한다. MPEG-4 호화 영상 및 MPEG-4 디블록킹 필터를 적용한 영상에 대해서 제안한 비선형 필터를 적용하여 주관적 화질이 개선됨을 실험을 통하여 보인다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.4
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• pp.41-49
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• 2008

H.264/AVC supports variable block motion compensation, multiple reference images, 1/4-pixel motion vector accuracy, and in-loop deblocking filter, compared with the existing compression technologies. While these coding technologies are major functions of compression rate improvement, they lead to high complexity at the same time. For the H.264 video coding technology to be actually applied on low-end / low-bit rates terminals more extensively, it is essential to improve tile coding speed. Currently the deblocking filter that can improve the moving picture's subjective image quality to a certain degree is used on low-end terminals to a limited extent due to computational complexity. In this paper, a performance improvement method of the deblocking filter that efficiently reduces the blocking artifacts occurred during the compression of low-bit rates digital motion pictures is suggested. In the method proposed in this paper, the image's spatial correlational characteristics are extracted by using the variable block information of motion compensation; the filtering is divided into 4 modes according to the characteristics, and adaptive filtering is executed in the divided regions. The proposed deblocking method reduces the blocking artifacts, prevents excessive blurring effects, and improves the performance about $30{\sim}40%$ compared with the existing method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.236-238
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• 2012

본 논문에서는 HEVC 코덱에서 프레임 단위로 수행되던 디블록킹 필터를 하드웨어 구현 시에 LCU 단위로 처리되는 파이프라인 구조를 적용하여 병렬적으로 수행할 수 있는 방법을 제안한다. 파이프라인 구조에서는 현재 처리되고 있는 하나의 LCU 에 대해 디블록킹 필터를 수행하기 위해서 현재 처리하고 있는 LCU 뿐만 아니라 주변의 LCU 의 화소 값 등의 정보가 필요하며 주변의 LCU 의 화소 값을 모두 저장하는 것은 불필요한 메모리소모를 야기해 HEVC 코덱의 복잡도를 증가시킬 수 있다. 또한 현재 처리되는 LCU 의 경계에 디블록킹 필터를 수행하는 경우 현재 처리되는 LCU 이전의 수정할 수 없는 LCU 의 화소 값도 수정되어야 한다. 따라서 본 논문에서는 이를 해결하기 위해 수평 버퍼 와 수직 버퍼의 개념을 도입하여 처리되는 LCU 의 왼쪽 LCU 의 오른쪽 끝 4 열의 화소와 위쪽 LCU 의 아래쪽 끝 4 행의 화소만을 저장하여 메모리를 합리적으로 사용하는 방법을 제시하고 평행이동 LCU 개념을 적용하여 수정 불가능한 화소 값들을 처리하는 방법을 제시한다. 제안된 구조에 따라 구현된 소프트웨어 상에서 기존의 참조 소프트웨어인 HM6.0 과 동일한 결과를 얻을 수 있었다.