• Journal of IKEEE
• /
• v.25 no.4
• /
• pp.625-633
• /
• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.8
• /
• pp.1172-1179
• /
• 2022

This paper describes a design of point scalar multiplier for public-key cryptography based on binary Edwards curves (BEdC). For efficient implementation of point addition (PA) and point doubling (PD) on BEdC, projective coordinate was adopted for finite field arithmetic, and computational performance was improved because only one inversion was involved in point scalar multiplication (PSM). By applying optimizations to hardware design, the storage and arithmetic steps for finite field arithmetic in PA and PD were reduced by approximately 40%. We designed two types of point scalar multipliers for BEdC, Type-I uses one 257-b×257-b binary multiplier and Type-II uses eight 32-b×32-b binary multipliers. Type-II design uses 65% less LUTs compared to Type-I, but it was evaluated that it took about 3.5 times the PSM computation time when operating with 240 MHz. Therefore, the BEdC crypto core of Type-I is suitable for applications requiring high-performance, and Type-II structure is suitable for applications with limited resources.

• KIPS Transactions on Software and Data Engineering
• /
• v.11 no.1
• /
• pp.51-58
• /
• 2022

Drivable area detection, one of the main functions of advanced driver assistance systems, means detecting an area where a vehicle can safely drive. The drivable area detection is closely related to the safety of the driver and it requires high accuracy with real-time operation. To satisfy these conditions, V-disparity-based method is widely used to detect a drivable area by calculating the road disparity value in each row of an image. However, the V-disparity-based method can falsely detect a non-road area as a road when the disparity value is not accurate or the disparity value of the object is equal to the disparity value of the road. In a road environment including vegetation, such as a highway and a country road, the vegetation area may be falsely detected as the drivable area because the disparity characteristics of the vegetation are similar to those of the road. Therefore, this paper proposes a drivable area detection method and hardware architecture with a high accuracy in road environments including vegetation areas by reducing the number of false detections caused by V-disparity characteristic. When 289 images provided by KITTI road dataset are used to evaluate the road detection performance of the proposed method, it shows an accuracy of 90.12% and a recall of 97.96%. In addition, when the proposed hardware architecture is implemented on the FPGA platform, it uses 8925 slice registers and 7066 slice LUTs.

• Journal of IKEEE
• /
• v.26 no.3
• /
• pp.510-514
• /
• 2022

In this paper, we propose the development of high-sensitivity low-end radiation measuring sensor module. The proposed measurement sensor module is a scintillator + photomultiplier(SiPM) sensor optimization structure design, amplification and filter and control circuit design for sensor driver, control circuit design including short-distance communication, sensor mechanism design and manufacturing, and GUI development applied to prototypes consists of, etc. The scintillator + photomultiplier(SiPM) sensor optimization structure design is designed by checking the characteristics of the scintillator and the photomultiplier (SiPM) for the sensor structure design. Amplification, filter and control circuit design for sensor driver is designed to process fine scintillation signal generated by radiation with a scintillator using SiPM. Control circuit design including short-distance communication is designed to enable data transmission through MCU design to support short-range wireless communication function and wired communication support. The sensor mechanism design and manufacture is designed so that the glare generated by wrapping a reflective paper (mirroring) on the outside of the plastic scintillator is reflected to increase the efficiency in order to transmit the fine scintillation signal generated from the plastic scintillator to the photomultiplier(SiPM). The GUI development applied to the prototype expresses the date and time at the top according to each screen and allows the measurement unit and time, seconds, alarm level, communication status, battery capacity, etc. to be expressed. In order to evaluate the performance of the proposed system, the results of experiments conducted by an authorized testing institute showed that the radiation dose measurement range was 30 𝜇Sv/h ~ 10 mSv/h, so the results are the same as the highest level among products sold commercially at domestic and foreign. In addition, it was confirmed that the measurement uncertainty of ±7.4% was measured, and normal operation was performed under the international standard ±15%.

• The Journal of the Korea Contents Association
• /
• v.22 no.9
• /
• pp.156-168
• /
• 2022

This study was conducted to investigate the staging principle, the staging work and the trial performance of Shingeuk troupe Geukyesulyeonguhoe during the period of coterie system, focusing on Gogol work·Ham Daehoon translation·Hong Haeseong directing's (5Act). As a result, the first trial performance was based on a faithful full-scale description rather than an interpretive directing of play. It was a performance that focused on copying and implanting the external form of the performance stage of Shingeki troupe Tsukiji Little Theater. The general review of the time was summarized to the point that it was a relatively successful performance that exceeded expectations as a trial demonstration of amateur actors. However, in terms of the content of play and the form of performance, reservations and lack of contemporary(modern) interpretation caused the problem that the general audience was alienated. Therefore, it was difficult to achieve the effect of reflecting the reality of Chosun through , as Geukyesulyeonguhoe intended.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.7
• /
• pp.1071-1077
• /
• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Journal of Korea Entertainment Industry Association
• /
• v.14 no.8
• /
• pp.287-294
• /
• 2020

The purpose of this study was, base on the observation that the leg movement has effect on muscles around trunk, to provide clinical fundamental data to develop effective abdominal draw-in technique by investigating the effect of abdominal draw-in exercise accompanying leg movement on the thickness of transversus abdominis muscle and trunk control ability in patients with stroke. The subjects were assigned randomly to experimental group I (n=9) on which the abdominal draw-in technique is applied and experimental group II (n=9) on which the abdominal draw-in technique accompanying leg movement is applied. The thickness of transversus abdominis muscle in the affected side and the trunk control ability were measured before and after treatment using ultrasonography and trunk impairment scale. A session of 30 minutes per day were performed four days a week for four weeks and the measured outcomes were analyzed. The in-group comparison showed significant difference both thickness of transversus abdominis muscle during abdominal draw-in technique application (p<0.01) and trunk control ability (p<0.001) between before and after treatment. The significant difference between two groups were observed only in trunk control ability (p<0.05). It was concluded that the abdominal draw-in technique accompanying leg movement is an intervention that has positive effect not only on transversus abdominis muscle but also on tunk control ability by inducing more efficient contraction reaction in muscles around trunk through autonomic pelvic movement caused by leg movement.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.33 no.5
• /
• pp.787-799
• /
• 2023

As IoT devices are widely used at home, IoT automation system that is integrate IoT devices for users' demand are gaining populrity. There is automation rule in IoT automation system that is collecting event and command action. But attacker delay the packet and make time that real state is inconsistent with state recongnized by the system. During the time, the system does not work correctly by predefined automation rule. There is proposed some detection method for delay attack, they have limitations for application to IoT systems that are sensitive to traffic volume and battery consumption. This paper proposes a practical packet delay attack detection technique that can be applied to IoT systems. The proposal scheme in this paper can recognize that, for example, when a sensor transmits an message, an broadcast packet notifying the transmission of a message is sent to the Server recognized that event has occurred. For evaluation purposes, an IoT system implemented using Raspberry Pi was configured, and it was demonstrated that the system can detect packet delay attacks within an average of 2.2 sec. The experimental results showed a power consumption Overhead of an average of 2.5 mA per second and a traffic Overhead of 15%. We demonstrate that our method can detect delay attack efficiently compared to preciously proposed method.

• Journal of the Korean Society of Radiology
• /
• v.17 no.7
• /
• pp.1133-1138
• /
• 2023

This study analyzed the relationship between image parameters and specific absorption rate (SAR) in various sequence environments to optimize SAR. For this purpose, image parameters were adjusted for T2, T1, STIR, T1 FLAIR, and T2 FLAIR sequences in a 3.0T MRI, and the whole body (WB) SAR and head SAR calculated by the device were measured. Then, the SAR was evaluated by adjusting the number of images and the flip angle (FA) of the refocusing RF. As a result, SAR increased as the number of image increased in all sequences. T1 and T1 FLAIR had correlation coefficients (r) of 0.876, 0.876 (WB SAR, head SAR), 0.867, 0.867 (WB SAR, head SAR), respectively, and STIR had the highest correlation with 0.898 and 0.899 (WB SAR, head SAR). showed (p<0.05). When applied by increasing the refocusing FA, WB SAR and head SAR increased overall in all sequences. The T1 and T2 sequences showed high correlation with correlation coefficients (r) of 0.897, 0.898 (WB SAR, head SAR) and 0.914, 0.915 (WB SAR, head SAR), respectively, while the sequences to which the inversion recovery technique was applied had relatively low FA, showed less sensitivity to increase. Therefore, in a sequence with a relatively low TR, minimizing the number of image and applying the fast spin echo to reduce the refocusing FA in a sequence with a high duty cycle are effective in reducing SAR.

• The Journal of the Acoustical Society of Korea
• /
• v.43 no.3
• /
• pp.314-323
• /
• 2024

Recently, a score-penalty method has been used for the acoustic passive tracking of marine mammals. The interesting aspect of this technique lies in the loss function, which has a penalty term representing the mismatch between the measured signal and the modeled signal, while the traditional time-domain matched-field processing is positively considering the match between them. In this study, we apply the score-penalty method into the depth estimation of a passive target with a known source waveform. Assuming deep ocean environments with uncertainties in the sound speed profile, we evaluate the score-penalty method, comparing it with the time-domain matched field processing method. We shows that the score-penalty method is more accurate than the time-domain matched field processing method in the ocean environment with weak mismatch of sound speed profile, and has better efficiency. However, in the ocean enviroment with strong mismatch of the sound speed profile, the score-penalty method also fails in the depth estimation of a target, similar to the time-domain matched-field processing method.