• Journal of the Korean Academy of Child and Adolescent Psychiatry
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• v.7 no.2
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• pp.190-202
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• 1996

This study assessed psychiatrically referred 5-to 13-year-old children who presented inattention or hyperactivity as chief complaints. Demographic characteristics, primary diagnosis, and comorbid psychiatric conditions of them were identified, and they were assessed using questionnaires and neuropsychological tests. Primary diagnoses included ADHD, anxiety disorder, mental retardation, depression, oppositional defiant disorder, developmental language disorder and others. functional enuresis, conduct disorder, and developmental language disorder were among the secondarily diagnosed disorders. In patients diagnosed as ADHD, overall comorbidity rate was 55.3%. The disorders that frequently co-occured with ADHD were specific developmental disorder, conduct disorder, oppositional defiant disorder, anxiety disorder and other. ADHD groups with or without comorbidity differed in performance IQ and CPT scores. ADHD group differed from externalizing disorders group in the information subscore of IQ, MFFT, and CPT scores, and differed in teachers rating scales, the uncommunication factor of CBCL, and CPT card error compared with internalizing disorders group. The authors concluded that inattentive or hyperactive children should be assessed using various instruments to differentiate other disorders and to identify possible presence of comorbid conditions.

• Journal of the Korean Academy of Child and Adolescent Psychiatry
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• v.7 no.2
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• pp.224-232
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• 1996

The present study was conducted to investigate cognitive characteristics of children with dyslexia and/or attention deficit/hyperacidity disorder. Cognitive characteristics were evaluated by using KEDI-WISC, the Basic Achievement Test, TOVA, MFFT, and neuropsychological tests. ADHD group showed significantly lower level of performance in response time for correct responses and presented variability for correct responses in TOVA. Dyslexia and mixed group showed lower performance in Reading I and Reading II, Writing subtest in the Basic Achievement Test than those of ADHD group and in Information subtest of KEDI-WfSC. In order rd determine the diagnostic effectiveness of each psychological tests, discriminant analysis was conducted. In this analysis, 11 subtests of KEDI-WISC and 4 variables of TOVA, 4 subtests of the Basic Achievement Test, and MFFT, WCST were included as independent variables and each diagnostic roups were dependent variables. Discriminant analysis indicated that overall percentage of correct classification was 93.88%. The clinical implifications and limitations of the present study were listed and discussed.

• The Journal of the Acoustical Society of Korea
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• v.24 no.8
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• pp.498-504
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• 2005

We introduce a Korean speech recognition platform (ECHOS) developed for education and research Purposes. ECHOS lowers the entry barrier to speech recognition research and can be used as a reference engine by providing elementary speech recognition modules. It has an easy simple object-oriented architecture, implemented in the C++ language with the standard template library. The input of the ECHOS is digital speech data sampled at 8 or 16 kHz. Its output is the 1-best recognition result. N-best recognition results, and a word graph. The recognition engine is composed of MFCC/PLP feature extraction, HMM-based acoustic modeling, n-gram language modeling, finite state network (FSN)- and lexical tree-based search algorithms. It can handle various tasks from isolated word recognition to large vocabulary continuous speech recognition. We compare the performance of ECHOS and hidden Markov model toolkit (HTK) for validation. In an FSN-based task. ECHOS shows similar word accuracy while the recognition time is doubled because of object-oriented implementation. For a 8000-word continuous speech recognition task, using the lexical tree search algorithm different from the algorithm used in HTK, it increases the word error rate by $40\%$ relatively but reduces the recognition time to half.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.128-136
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• 2002

In this paper, we developed an acoustic echo canceller in real-time using TeakLite DSP Core, which will be placed in the vocoder chip of a mobile handset. Considering the limited computational capacity given to the acoustic echo canceller in a vocoder chip, we employed a FIR-type adaptive filter using a conventional NLMS algorithm. To begin with, we designed and implemented an acoustic echo canceller with floating-point format C-source code, and then converted it into fixed-point format through integer simulation. Then we programmed and optimized it in the assembler level to make it run ill real-time. After optimization procedure, the implemented echo canceller has approximately 624 words of program memory and 811 words of data memory. With 8 KHz sampling rate and 256 filter taps in the echo canceller that corresponds to 32 msec of echo delay, it requires 14.12 MIPS of computational capacity. For coverage of 16 msec echo delay, i.e., 128 filter taps, 9 MIPS is requited.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.421-429
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• 2000

In present, ATM integrated switching system has been developed to a mixed modules that complexed switching system including maintenance, operation based on B-ISDN/LAN service and plug-in module, , which runs on workstation computer system. Meanwhile, workstation has HMI operation system feature including file system management, time management, graphic processing, TMN agent function. The workstation has communicated with between ATM switching module and clients. This computer system architecture has much burden messages communication among processes or processor. These messages communication consume system resources which are socket, message queue, IO device files, regular files, and so on. Therefore, in this paper we proposed new performance modeling with this system architecture. We will analyze the system bottleneck and improve system performance. In addition, in the future, the system has many additional features should be migrated to workstation system, we need previously to evaluate system bottleneck and redesign it. In performance model, we use queueing network model and the simulation package is used PDQ and C-program.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.62-71
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• 2001

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.1 no.1
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• pp.6-25
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• 2002

In this paper, we have implemented UPnP Devices which emulate a Control Point, a Light Controller, and a Digital TV. The Control Point has been developed on Linux host system by using C language. The UPnP Devices emulating the Digital TV and Light Controller are running on embedded linux developer board. For the development of UPnP Devices, UPnP SDK API Vl.04 made by Intel Co. Ltd. has been ported on Assabet Linux Reference board to implement the UPnP protocol. After we analyze and design some services of Digital TV device, we have applied UPnP Device program to those devices. UPnP SDK vl .04 consists of APIs which support HTTP, SSDP, SOAP, GENA and XML DOM Level-1 that are cores of UPnP protocol. The C program written for the UPnP Control Point has been compiled and executed on Linux-based PC. The embedded system running on Embedded Linux OS has been connected all together through Ethernet which allows IP-based communications. Under this environment, the UPnP programs are being executed on each device. Control Point, when in operational mode, discovers UPnP Devices on the network and displays the device list on the consol. By selecting one of the functionalities of the device services that are displayed on the Control Point, the controllability has been accomplished. The experiment that we performed in this thesis have revealed that the Control Point and UPnP Devices have supported the protocols including SSDP, SOAP, GENA, and DHCP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.