• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.451-452
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• 2009

IEEE 1588은 대칭 망에서만 정확한 클럭 동기화를 제공하는 문제점이 있다. 이를 해결하기 위해 Enhanced IEEE 1588이 제안되었지만, 단순히 비대칭 링크 율만을 고려했다는 한계를 가진다. 본 논문에서는 비대칭 율이 매우 크며 클럭 동기화 정확성에 영향을 미칠 수 있는 요소를 사용한 비대칭 망 환경에서도 정확한 클럭 동기화를 제공할 수 있는 새로운 알고리즘을 제안한다.

• Journal of Korea Multimedia Society
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• v.15 no.11
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• pp.1391-1398
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• 2012

Time synchronization is crucial in wireless sensor networks such as Wireless USB and WBAN for diverse purposes from the MAC to the application layer. This paper proposes online clock skew estimators to achieve energy-efficient time synchronization for wireless sensor networks. By using recursive least squares estimators, we not only reduce the amount of data which should be stored locally in a table at each sensor node, but also allow offset and skew compensations to be processed simultaneously. Our skew estimators can be easily integrated with traditional offset compensation schemes. The results of simulation and experiment show that the accuracy of time synchronization can be greatly improved through our skew compensation algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.2062-2073
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• 1997

The important articles we must consider in SDH network and system design are the number of maximum nodes and clock characteristics of each node. In order to get these, the study of characteristics about some clock states, such as normal state and phase transient state, on the standard specifications is required. In this paper, we presented MTIE and TDEV characteristics with ITU-T & ANSI standard specifications in some clock states of the SDH linear networks, and proposed the number of maximum nodes satisfying above two standards. Also our resulsts are compared with AT&T's.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.11a
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• pp.335-342
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• 2000

멀티미디어 정보를 처리하기 위해서 필수적으로 필요한 기술이 멀티미디어 동기화를 구성하는 것이다. 본 논문에서는 두 시스템 사이의 클럭 동기를 맞추어 주기 위하여 가상 클럭(VGC : Virtual Global Clock)을 제안하였다. Loop flack 방법에 의한 제안된 가상 클럭은 통신이 가능한 모든 환경에 적용할 수 있다

• ETRI Journal
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• v.8 no.2
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• pp.45-52
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• 1986

교환망이 점차로 디지틀화 되면서 네트워크내의 클럭 주파수의 불일치에 의해 야기되는 slip 발생에 따른 정보손실은 중요한 문제점으로 대두되었으며 모든 디지틀 교환기는 네트워크내의 기준 주파수에 자체 클럭을 동기시키기 위한 망동기 기능을 수용하며 silp 발생을 방지하고 있다. TDX-1에서는 국내 교환망 동기 체계에 적합한 동기회로계를 개발하여 망동기를 성취하고 있으며 본고는 이 회로계의 특성에 대해 논하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6B
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• pp.305-315
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• 2007

In this paper, We generated a wander generation model from really measured clock noise data on the transmission node and DOTS in NG-SDH network. and then, We presented the performance of Synch. clock and maximum node level capable network configuration through the clock characteristics simulation on network having the steady-state clock.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• The KIPS Transactions:PartC
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• v.13C no.3 s.106
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• pp.303-310
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• 2006

This paper is to execute a study for characteristic analysis of synchronization clock and maximum network node number with various clock states, normal, SPT, LPT, in NG-SDH networks. Through the simulations, maximum network node numbers showed from 42 to 38 nodes in normal state. In SPT state, maximum network node numbers, when the last NE network applied to only SPT state, presented from 19 to 4 nodes, much less than normal state. Node numbers to meet specification in case of occurrence of SPT state in all NE networks decreased greatly. In LPT state, all maximum node numbers, when the last NE network applied to only LPT state, presented more than 50 nodes, and the results in case of occurrence of LPT state in all NE networks were also identified. However, node numbers to meet specification in case of LPT state in all DOTS networks were few large with difference between LPT and normal or SPT state.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1765-1773
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• 1997

The communication systems which include PLL may have cycle clip problem because of channel noise. The cycle slip problem occurs the synchronization loss of communication system and it may be fatal to the synchronous stream cipher system. While continuous resynchronization is used to lessen the risk of synchronization it has some problems. In this paper, we propose the method which solve the problems by using continuous resynchronization with the clock recovery technique. If the counted value of real clock pulse in reference duration is not same as that of normal state, we decide the cycle slip has occurred. The damaged clock by cycle slip is compensated by adding or subtracting the clock pulse according to the type of cycle slip. It reduced the time for resynchronization by twenty times. It means that 17.8% of data for transmit is compressed.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.746-749
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• 2009

유비쿼터스 센서 네트워크에서 사용되는 센서노드는 동종의 센서 노드와 많은 수의 이기종 센서 노드들을 포함하게 된다. 이기종 센서노드들간의 시간동기화로 인한 배터리 전력소모를 최소화하기 위해서 본 논문에서는 싱크노드 아래에 있는 싱크노드와 클럭소스가 같은 동종 센서노드를 시간동기 마스터로 설정하고, 싱크노드와 다른 클럭소스를 가지는 다수의 이기종 센서노드를 마스터 아래에 속하는 시간동기 슬레이브로 설정하여 시간동기 마스터가 동작을 개시할 때에만 시간동기 슬레이브 노드들이 동작하도록 동기화하는 이기종 센서노드들의 시간동기화 기법을 제안한다.