• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.952-955
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• 2015

본 연구는 현재 스마트폰 모델을 조립하는 공정에서 카메라 렌즈 부품을 조립하는 수동으로 팔레트 위에 위치한 부품의 좌표를 수동으로 입력하고 검증하는 과정으로 소형 델타로봇에 스마트 액추에이터와 초소형 비전 카메라를 장착하여 렌즈부품의 위치좌표를 자동으로 검출하고, 빠르고 정확하게 타겟팅된 위치로 이동시킬 수 있는 자동타게팅 델타로봇 시스템을 개발하는 것이다.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.72-76
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• 2004

본 논문에서는 일명 델타변환 무정전전원장치(UPS)로서 알려져 있는 3상 라인 인터랙티브 UPS 시스템의 성능 시험에 대해서 다루고 있다. 델타변환 UPS는 종래의 단일 변환 라인 인터랙티브 UPS 시스템에서 직렬 인덕터를 제거하고 직렬 및 병렬 PWM 컨버터를 사용하는 새로운 라인 인터랙티브 UPS 시스템으로 전원 전류를 직접 제어함으로써 UPS 시스템의 입출력 특성들이 상당히 개선되는 것으로 알려져 있다. 여기서는 UPS 시스템의 성능 시험에서 중요한 내용들인 부하시험, 정전/복전시험, 동기절체 시험 등에 대한 결과들을 제시하고 델타변환 UPS 시스템에 대한 전반적인 평가를 한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.405-408
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure, which is a type of an IIR filter. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.633-648
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• 1998

Rapid computing environment, change of the application structure, and various user demand will increase the demand of the software development. Version control is helpful to improve productivity using delta, and useful to establish component from existing data of source code. This paper presents the design and implementation of the version control system. which is composed of retrieval system and delta management system. In retrieval system, vanous retrieve methods arc proposed. This methods provides the process methodology with filename, content, size and date. Various retrieve methods arc important for the effective delta management. Meta data can be easily composed for the delta management by these methods. Compared with other systems, this implemented version control system has some advantage. First, for delta management, version maintenance for delta management becomes easier by integrating the forward and back-ward methods. Second, delta managent part of a project is to unite the forward and backward method. the effieiency of this system is to increased in management. Also, this system supports a thechnique of using the database and files for project repository and makes the version management more effective.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.6-12
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• 2010

A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.02a
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• pp.109-112
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• 2008

본 논문에서는 MPEG-4 HE-AAC의 SBR 부호기의 효율을 개선하기 위해 예측 SBR(Predictive-SBR)을 제안한다. SBR 부호기는 주부호기(core encoder)와 결합하여 적은 비트량으로 고주파 성분을 복원할 수 있게 한다. 본 논문에서는 SBR 데이터의 약 70%를 차지하는 포락선 정보를 부호화하는 방법을 개선하여 효율성을 높이고자 한다. 기존 SBR은 포락선 정보의 전송을 위해 다음과 같은 방법을 이용한다. 먼저 고주파 대역의 에너지를 스케일팩터 밴드 단위로 계산한다. 다음으로, 전송정보량의 감소를 위해 델타 코딩 방식을 이용하여 에너지 정보를 부호화한다. 본 논문에서는 SBR의 포락선 정보를 효과적으로 감축하기 위하여 고주파 대역의 에너지를 예측하는 방법을 이용한다. SBR 부호기의 입력 데이터가 SBR 복호기의 입력데이터와 동일하다는 가정 하에 선형 회귀(linear-regression) 기법을 이용하여 고주파 대역의 에너지를 추정한다. 그 후에 추정된 에너지와 원래의 고주파 대역 에너지의 오차를 델타 코딩을 이용하여 부호화한다. 정보를 전송할 때는 고주파 대역 에너지의 델타 코드와 예측 SBR에서 계산한 오차의 델타 코드 중 부호화에 필요한 비트량이 적은 방식을 선택하여 부호화하도록 한다. 그 결과 약 10% 정도의 정보량 감축 효과를 얻을 수 있다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.76-82
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• 2004

A method of designing a state feedback gam achieving a specified insensitivity of the closed-loop trajectory by the singularly perturbed unified system using the operators is proposed. The order of system is reduced by the singular perturbation technique by ignoring the fast mode in it. The proposed method takes care of the actual trajectory variations over the range of the singular perturbation parameter. Necessary conditions for optimality are also derived. The previous study was done in the continuous time system The present paper extends the previous study to the discrete system and the ${\delta}-operating$ system that unifies the continuous and discrete systems. Advantages of the proposed method are shown in the numerical example.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.2
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• pp.712-717
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• 2011

Option issuers generally utilize Dynamic Delta Hedging(DDH) technique to avoid the risk resulting from continuously changing option value. DDH duplicates payoff of option position by adjusting hedge position according to the delta value from Black-Scholes(BS) model in order to maintain risk neutral state. DDH, however, is not able to guarantee optimal hedging performance because of the weaknesses caused by impractical assumptions inherent in BS model. Therefore, this study presents a methodology for dynamic option hedge using artificial neural network(ANN) to enhance hedging performance and show the superiority of the proposed method using various computational experiments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.