• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.719-726
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• 2015

As big-data and cloud security technologies become popular, many researchers have recently been conducted on faster and lighter encryption. As a result, National Security Research Institute developed LEA which is lightweight and fast block cipher. To date, there have been various studies on lightweight encryption algorithm (LEA) for speeding up using GPU rather than conventional CPU. However, it is rather difficult to explore any guideline how to manipulate the GPU for the efficient usage of the LEA. Therefore, we introduce a guideline which explains how to implement and design the optimal LEA using GPU.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.8
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• pp.372-378
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• 2001

오늘날, 이질적인 분산 컴퓨팅 환경을 통합하고 분산 공유 자원을 효율적으로 사용할 수 있는 공통 작업 환경에 대한 요구가 날로 높아지고 있다. 이러한 연구 중에서 주목받는 것 중 하나가 OMG의 CORBA이다. CORBA 시스템에서 실시간 멀티미디어 데이터들을 처리하기 위해 확장된 CORBA 표준을 RT(Real-Time) CORBA라고 한다. RT CORBA의 핵심은 수많은 실시간 태스크들의 블록을 최대한 방지하여 실시간 QoS를 보장해 줄 수 있는 실시간 스케쥴링 기법에 있다고 할 수 있다. 현재 RT CORBA를 위해 제안되는 많은 스케쥴링 기법들은 대개 이전의 단일 시스템에 기반한 전역 우선순위 기반 스케쥴링이 대부분이다. 하지만 이러한 Soft Real-Time 스케쥴링은 다양한 성능 요소가 산재하는 분산 시스템에서는 그 성능을 보장할 수 없다. 본 논문에서는 CORBA와 같은 분산시스템의 보편적 특성을 고려한 Hard Real-Time 스케쥴링 기법인 CII(Cut In Interval) 기법을 제안하였다. 기존의 전역 우선순위 바탕의 스케쥴링이 비효율적인 태스크 할당 및 지역 스케쥴링을 제공하지만, CII 기법의 스케쥴링은 간단하면서도 보다 효과적인 전역 스케쥴링을 제공할 수 있다. CII 기법의 핵심은 이미 스케쥴링된 태스크를 가능한 제한시간까지 연기하여 얻어진 여유시간을 다른 실시간 태스크들의 처리에 활용하자는 것이다. 이러한 여유시간의 활용은 제안한 기법이 기존의 기법과 달리 보다 능동적이고 효율적인 스케쥴링 기법임을 증명한다.

• Journal of the Korea Society of Computer and Information
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• v.13 no.7
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• pp.117-126
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• 2008

Recent advances in medical imaging technologies have enabled the high-resolution data acquisition. Therefore visualization of such large data set on standard graphics hardware became a popular research theme. Among many visualization techniques, we focused on bricking method which divided the entire volume into smaller bricks and rendered them in order. Since it switches bet\W8n bricks on main memory and bricks on GPU memory on the fly, to achieve better performance, the number of these memory swapping conditions has to be minimized. And, because the original bricking algorithm was designed for regular volume data such as CT and MR, when applying the algorithm to ultrasound volume data which is based on the toroidal coordinate space, it revealed some performance degradation. In some areas near bricks' boundaries, an orthogonal viewing ray intersects the single brick twice, and it consequently makes a single brick memory to be uploaded onto GPU twice in a single frame. To avoid this redundancy, we divided the volume into bricks allowing overlapping between the bricks. In this paper, we suggest the formula to determine an appropriate size of these shared area between the bricks. Using our formula, we could minimize the memory bandwidth. and, at the same time, we could achieve better rendering performance.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.535-542
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• 1995

In this paper we present two preconditioners for solving large sparse linear systems arising from elliptic partial differential equations on massively parallel machines, such as the CM-5. Most massively parallel machines do heavily rely on the message-passing for the interprocessor communications. but according to the current manufacturing standards the cost of communications is very high compared to that of floating point arithmetic computations. Due to this we need an algorithm which minimizes the amount of interprocessor communication on the massively parallel machines. We will show that Block SOR(Successive Over Relaxation) method coupled with the multi-coloring technique is one of such preconditioner on the massively parallel machines, by conducting experiments in the CM-5. Also, we implemented the ADI(Alternation Direction Implicit) method in the CM-5, which has been conventionally one of the most powerful parallel preconditioner. Our experiment shows that Block SOR method coupled with the multi-coloring technique could yield a speedup with 50% efficiency with the range of number of processors form 16 to 512 for a matrix with dimension 512x512. On the other hand, the ADI method shows a very poor performance.

• Composites Research
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• v.36 no.5
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• pp.361-368
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• 2023

Composite materials used in aircraft must be certified using approved materials to ensure the the airworthiness of the aircraft. Certification is carried out by verifying the physical properties and processes of the materials, and producing material and process specifications. The composite material certification system in ROK(Republic of Korea) has been established through the MOLIT(Ministry of Land, Infrastructure and Transport) pilot certification project for aircraft composite materials. Currently, the KIAST(Korea Institute of Aviation Safety Technology) operates and manages the certification and shared data system. This study identifies realm for improvement in the established certification system for aircraft composite materials based on empirical evidence and aims to propose measures for the certification and industrial promotion of domestically produced aircraft composite materials.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Industry Promotion Research
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• v.8 no.2
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• pp.21-27
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• 2023

This study studies the policies and use cases of the government and the financial sector for artificial intelligence, and the future policy tasks of the financial sector. want to derive According to Gartner, noteworthy technologies leading the financial industry in 2022 include 'generative AI', 'autonomous system', 'Privacy Enhanced Computation (PEC) was selected. The financial sector is developing new technologies such as artificial intelligence, big data, and blockchain. Developments are spurring innovation in the financial sector. Data loss due to the spread of telecommuting after the corona pandemic As interests in sharing and personal information protection increase, companies are expected to change in new digital technologies. Global financial companies also utilize new digital technology to develop products or manage and operate existing businesses. I n order to promote process innovation, I T expenses are being expanded. The financial sector utilizes new digital technology to prevent money laundering, improve work efficiency, and strengthen personal information protection. are applying In the era of Big Blur, where the boundaries between industries are disappearing, the competitive edge in the challenge of new entrants In order to preoccupy the market, financial institutions must actively utilize new technologies in their work.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.12
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• pp.2213-2220
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• 2017

This paper proposes an efficient approach for hardware implementation of moving object detection (MOD) processor using effective Gaussian mixture learning (EGML)-based background subtraction method. Arithmetic units used in background generation were implemented using LUT-based approximation to reduce hardware complexity. Hardware resources used for both background subtraction and Gaussian probability density calculation were shared. The MOD processor was verified by FPGA-in-the-loop simulation using MATLAB/Simulink. The MOD performance was evaluated by using six types of video defined in IEEE CDW-2014 dataset, which resulted the average of recall value of 0.7700, the average of precision value of 0.7170, and the average of F-measure value of 0.7293. The MOD processor was implemented with 882 slices and block RAM of $146{\times}36kbits$ on Virtex5 FPGA, resulting in 60% hardware reduction compared to conventional design based on EGML. It was estimated that the MOD processor could operate with 75 MHz clock, resulting in real-time processing of $800{\times}600$ video with a frame rate of 39 fps.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.675-688
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• 2007

Memory access errors are frequently occurred in C programs. A number of tools and research works have been trying to detect the errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, incompatibility with libraries, and excessive performance overhead. In this paper, we suggest a new method to solve these problems, and then present a result of comparison to the previous research works through the experiments. Our approach consists of two phases. First is to transform source code at compile time through inserting instrumentation into the source code. And second is to detect memory errors at run time with a bitmap that maintains information about memory allocation. Our approach has improved the error detection abilities against the binary code analysis based ones by using the source code analysis technique, and enhanced performance in terms of both space and time, too. In addition, our approach has no problem with respect to compatibility with shared libraries as well as does not need to modify memory allocation mechanism.