• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.1-9
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• 2020

In this paper, we propose an efficient adaptive write scheme that improves the performance of write operation in MLC STT-MRAM caches. The key idea of the proposed scheme is to perform the write operation fast if the target MLC STT-MRAM cells contain a dead block. Even if the fast write operation on the MLC STT-MRAM evicts a cache block from the MLC STT-MRAM cells, its performance impact is low if the evicted block is a dead block which is not used in the future. Through experimental evaluation with a memory simulator, we show that the proposed adaptive write scheme improves the performance of the MLC STT-MRAM caches by 17% on average.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.473-476
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• 2001

본 논문에서는 HOL 블록킹 현상과 데드락을 줄이기 위해 공유 메모리 스위치를 이용하고 셀에 형태에 따라 유니캐스트 셀과 멀티캐스트 셀을 따로 저장하는 방법을 이용하여 셀의 부하를 줄이는 멀티캐스트 ATM 스위치를 제안한다. 그리고, 트래픽 셀의 손실을 줄이고, 효과적으로 출력하기 위해 제어부에서 출력 포트에 따라 스케줄링하는 기법을 택하였다. 제안한 스위치의 성능을 시뮬레이션을 통해 그 유효성을 보였다.

• Proceedings of the Korea Contents Association Conference
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• 2007.11a
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• pp.837-841
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• 2007

최근 영상을 중심으로 여러 형태의 정보를 결합하여 저장하거나 전송하는 멀티미디어가 많은 관심을 받고 있다. 현재 카메라와 관련된 동영상 캡처기술은 Motion JPEG이 주류를 이루고 있으며, 텔레비전, DMB 등의 방송 분야 및 DVD, VCR 분야에서는 MPEG-2, MPEG-4, H.264 및 WMV9 등의 압축 코덱이 채용되고 사용되고 있다. 그러나 이러한 다양한 영상 표준방식은 디코딩시 호환성 문제가 발생하게 되고 이에 따라 통합 코덱 연구가 필요하다. 이에 본 논문은 일반적 스텝 양자화외에 데드존 양자화를 사용하고 "$4{\times}4$", "$4{\times}8$", "$8{\times}4$", "$8{\times}8$"의 다양한 블록크기의 변환을 지원하는 VC-1을 기반으로 한 ITIQ C언어를 통해 시뮬레이션하고 최적화된 결과를 VHDL로 구현하여 향후 통합코덱 연구에 응용 가능하도록 연구 및 분석평가 하였다. 설계결과 4:2:0의 YCbCr포맷의 최초 $16{\times}16$블록을 복원하는데 483~510클록이 소요되었고 Xilinx XCVPC100 FF1696-6 환경에서 93,128개의 게이트 수와 71.469MHz의 동작속도를 나타내었다. 이는 640*480 크기의 컬러영상을 디코딩 하는데 프레임 당 최대 0.0074초가 소요됨을 의미하며 초당 30프레임의 영상에서도 0.222초면 디코딩이 가능한 결과이다.

• Journal of Korea Multimedia Society
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• v.6 no.2
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• pp.301-308
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• 2003

In this paper, we propose a multicast ATM switch that reduces traffic load by using the method of storing unicast cells and multicast cells separately according to the type of the cells. The switch is based on a shared memory type to reduce HOL blocking and deadlock. In the proposed switch, we use a control scheme that schedules stored cells to output ports to reduce the loss of traffic cells and to output effectively. We analyzed the Performance of the proposed switch through the computer simulation and the results have shown the effectiveness of the switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1922-1931
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• 1999

A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.

• Journal of Internet Computing and Services
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• v.1 no.2
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• pp.11-18
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• 2000

In this paper we present a new extensible model based upon the concept of subtransactions in real-time transaction systems. The nested transaction model originally proposed by J. Moss is extended for real-time uniprocessor transaction systems by adding explicit timing constraints. Based upon the model, an integrated concurrency control and scheduling algorithm is developed, that not only guarantees timing constraints of a set of real-time transactions but also maintains consistency of the database. The algorithm is based on the priority ceiling protocol of Sha et al. We prove that the Real-Time Nested Priority Ceiling Protocol prevents unbounded blocking and deadlock, and maintains the serializability of a set of real-time transactions. We use the upper bound on the duration that a transaction can be blocked to show that it is possible to analyze the schedulability of a transaction set using rate-monotonic priority assignment. This work is viewed as a step toward multiprocessor and distributed real-time nested transaction systems. Also, it is possible to be extended to include the real-time multimedia transactions in the emerging web-based database application areas.