• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.97-104
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• 2004

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.2
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• pp.17-25
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• 2003

In this paper, a processor architecture is proposed based on the state space implementation technique for real time processing of 2-D discrete wavelet transform(DWT). It conducts 2-D DWT operations in consideration of row and column direction simultaneously, thus can reduce latency due to memory access for storing intermediate results. It is a VLSI architecture suitable for real time processing. The proposed architecture includes only four multipliers and four adders, and NK-N internal memory storage, where K denotes the length of filter. It has a small hardware complexity. Therefore it is very suitable architecture for real time, embedded applications such as web camera server. Since the processor is easily extended to array structure, it can be applied to various image processing applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11B
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• pp.965-971
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• 2003

This paper suggests a low-complexity frame timing synchronization system for IEEE802.11a wireless LAN systems. The proposed timing synchronization scheme has been implemented by correlating the received OFDM preamble with quantized coefficients composed of ｛0, ${\pm}$2$^{0}$ , ${\pm}$2$^1$‥‥‥ ${\pm}$2$^{i}$ ), where i is an integer number. The 2$^{i}$ -valued coefficients enable the multipliers in the correlation system to be simplified to i-bit shifters. So we can design the correlation system using shifters instead of multipliers. We estimate the performance of the proposed scheme in comparison with conventional systems under the AWGN and Rayleigh fading channels. In this paper we show that the complexity can be reduced by 90% while still maintaining a performance comparable to that of the conventional system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.10
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• pp.1403-1408
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• 2021

Recently, FPGA-based AI processors are being studied actively. Deep convolutional neural networks (CNN) are basic computational structures performed by AI processors and require a very large amount of multiplication. Considering that the multiplication coefficients used in CNN inference operation are all constants and that an FPGA is easy to design a multiplier tailored to a specific coefficient, this paper proposes a methodology to optimize the multiplier. The method utilizes 2's complement and distributive law to minimize the number of bits with a value of 1 in a multiplication coefficient, and thereby reduces the number of required stacked adders. As a result of applying this method to the actual example of implementing CNN in FPGA, the logic usage is reduced by up to 30.2% and the propagation delay is also reduced by up to 22%. Even when implemented with an ASIC chip, the hardware area is reduced by up to 35% and the delay is reduced by up to 19.2%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.3
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• pp.33-44
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• 2008

The efficiency of pairing based cryptosystems depends on the computation of pairings. pairings is defined over finite fileds GF$(3^m)$ by trinomials due to efficiency. The hardware architectures for pairings have been widely studied. This paper proposes new adder and multiplier for GF(3) which are more efficient than previous results. Furthermore, this paper proposes a new unified adder-subtractor for GF$(3^m)$ based on the proposed adder and multiplier. Finally, this paper proposes new multiplier for GF$(3^m)$. The proposed MSB-first bit-serial multiplier for GF$(p^m)$ reduces the time delay by approximately 30 % and the size of register by half than previous LSB-first multipliers. The proposed multiplier can be applied to all finite fields defined by trinomials.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.16-18
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• 2002

고속 회로 합성에 있어서, Wallace 트리 스타일은 연산을 위한 가장 효율적인 수행 방식의 하나로 인식 되어졌다. 그러나, 이러한 방법은 빠른 곱셈기의 수행이나 여러가지 연산수행 에 있어, 입력 시그널을 고려하지 않은 일반적인 구조로 수행되어졌다. 본 논문은 연산기에 있어서 이러한 제한점을 극복하는 문제를 다룬다. 우리는 캐리-세이브 방법을 덧셈, 뺄셈, 곱셈 이 혼합되어 있는 일반적인 연산 회로에 적용한다. 그 결과 효율적인 회로를 생성하며, 시그널 들의 임의의 시그널 스위칭 변화에 대해 회로의 전력 소모를 최적화 한다. 우리는 이러한 최적화 방법을 여러 디지털 필터에 적용시켜 보았고 이는 기존의 비트 단위가 아닌 캐리-세이브 수행방법보다 상당한 양의 전력 소모의 향상을 보였다.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1397-1398
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• 2008

본 논문에서는 BPSK 수신을 위한 덧셈(sum) 방식의 4-port 직접 변환 수신기를 제안하고, 국부 발진기(LO) 전력의 크기에 대한 수신기의 성능을 분석하였다. 수신 성능 분석에는 열잡음, 전력 검출기의 산탄(shot) 잡음, LO의 위상 잡음을 고려하였다. 수신 성능 분석 결과 최적의 신호대 잡음비를 보이는 최적의 LO 전력이 존재할 수 있음을 보였다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.