• Title/Summary/Keyword: 단자

Search Result 827, Processing Time 0.032 seconds

Subthreshold Current Model for Threshold Voltage Shift Analysis in Junctionless Cylindrical Surrounding Gate(CSG) MOSFET (무접합 원통형 게이트 MOSFET에서 문턱전압이동 분석을 위한 문턱전압이하 전류 모델)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.21 no.4
    • /
    • pp.789-794
    • /
    • 2017
  • Subthreshold current model is presented using analytical potential distribution of junctionless cylindrical surrounding-gate (CSG) MOSFET and threshold voltage shift is analyzed by this model. Junctionless CSG MOSFET is significantly outstanding for controllability of gate to carrier flow due to channel surrounded by gate. Poisson's equation is solved using parabolic potential distribution, and subthreshold current model is suggested by center potential distribution derived. Threshold voltage is defined as gate voltage corresponding to subthreshold current of $0.1{\mu}A$, and compared with result of two dimensional simulation. Since results between this model and 2D simulation are good agreement, threshold voltage shift is investigated for channel dimension and doping concentration of junctionless CSG MOSFET. As a result, threshold voltage shift increases for large channel radius and oxide thickness. It is resultingly shown that threshold voltage increases for the large difference of doping concentrations between source/drain and channel.

Seismic Control of Stiffness-degrading Inelastic SDOF Structures with Fully Elasto-Plastic Dampers (강성저감형 비탄성 단자유도 구조물에 설치된 완전탄소성 감쇠기의 제진성능)

  • Park, Ji-Hun;Kim, Hun-Hee;Kim, Ki-Myon
    • Journal of the Earthquake Engineering Society of Korea
    • /
    • v.14 no.4
    • /
    • pp.37-48
    • /
    • 2010
  • The seismic control effect of reinforced concrete structures with low energy dissipating capacity due to stiffness degradation is investigated through nonlinear time history analysis. The primary structure is idealized as a SDOF system of modified Takeda hysteresis rule and an elasto-perfectly-plastic nonlinear spring is added to represent a hysteretic damping device. Based on statistics of the numerical analysis, equivalent linearization techniques are evaluated, and empirical equations for response prediction are proposed. As a result, estimation of the ductility demand with proposed empirical equations is more desirable than the equivalent linearization techniques. The optimal yield strengths based on empirical equations are significantly different from the optimal yield strength of elasto-perfectly-plastic systems. Also, the results indicate that the reduction effect of the ductility demand is more remarkable for smaller natural periods.

Inelastic Displacement Ratio for Strength-limited Bilinear SDF Systems (강도한계 이선형 단자유도 시스템의 비탄성 변위비)

  • Han, Sang-Whan;Lee, Tae-Sub;Seok, Seung-Wook
    • Journal of the Earthquake Engineering Society of Korea
    • /
    • v.14 no.4
    • /
    • pp.23-28
    • /
    • 2010
  • This study evaluated the effect of vibration, level of lateral yielding strength, site conditions, ductility factor, strain-hardening ratio, and post-capping ratio of the strength limited bilinear SDF systems on the inelastic displacement ratio. The nonlinear response history analysis was conducted using 240 ground motions which were collected at the sites classified as site classes B, C, and D according to the NEHRP. To account for the P-$\Delta$ effects, this study considered negative stiffness ratios ranging from -0.1 to -0.5 of elastic stiffness. Four different damping ratios are used: 2, 5, 10, and 20%. From this study, an equation of inelastic displacement ratio was proposed using nonlinear regression analysis.

A study on how to discriminate the polarities of stator windings for 3 phase induction motors by using general purpose multi-testers (멀티테스터를 이용한 3상유도전동기 고정자 권선의 극성 판별법에 관한 연구)

  • Choi, Soon-Man
    • Journal of Advanced Marine Engineering and Technology
    • /
    • v.38 no.9
    • /
    • pp.1137-1140
    • /
    • 2014
  • Faulty electric motors onboard vessels with anomalies in windings or poor insulation are usually repaired at land based workshops and reinstalled in place by crew hands after receiving the repaired motors. Especially for 3 phase induction motors which need Y-${\delta}$ starters with 6 lead wires, it would happen that the polarities of stator windings cannot be well distinguished if the original tags of these wires are erased or not visible clearly, resulting in subsequent damage to the repaired motor due to extreme current flow when the power is given to the motor the stator windings of which are wrongly connected in the polarity. This study proposes an easy way to make correct connection in winding polarities without failures based on the electro-magnetically induced voltages on windings when a slight DC current is supplied to a winding coil by using an analog multi-tester. The proposed method is applied to actual motors and delves into the applicability for polarity discrimination through a few measurements onboard vessels.

A Delta Modulation Method by Means of Pair Transistor Circuit (쌍트랜지스터 회로에 의한 정착변조방식)

  • 오현위
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.8 no.2
    • /
    • pp.24-33
    • /
    • 1971
  • A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

  • PDF

A Study on Chopper Circuit for Variation of Inductance and Threshold Voltage based on IGBT (IGBT 기반 인덕턴스 및 문턱전압 변화에 따른 초퍼 회로의 연구)

  • Lho, Young-Hwan
    • Journal of the Korean Society for Railway
    • /
    • v.13 no.5
    • /
    • pp.504-508
    • /
    • 2010
  • The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide under the environment that radiation exists. The energy loss will be also studied as the inductance values are changed. In this paper, the electrical characteristics are simulated by SPICE, and compared for variation of inductance and threshold voltage based on IGBT.

New Packaging and Characteristics of PIN PD for CWDM Transmission (저밀도 파장분할 다중화용 PIN PD 제작 및 특성)

  • Kang, Jae-Kwang;Chang, Jin-Heyon
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.12 no.4 s.37
    • /
    • pp.323-330
    • /
    • 2005
  • We fabricate PIN PD (Positive Intrinsic Negative Photo-Diode) for CWDM optical repeater and optical transmission system, and analyze theoretically the characteristics to verify the capability of device fabricated. Furthermore, we integrate CWDM filter into PD package to enhance the cost and the performance when compared to the conventional system, in which CWDM filter and PD package are linked by optical fusion splicing. The integrated CWDM PD is fabricated by three steps as follows: CWDM filter design, PD packaging, and product assembly and test. The results of measurement for PD fabricated reveal 0.5 dB bandwidth of 17 nm, isolation over 60 dB at transmission port and over 20 dB at reflection port. Also, the IMD3 for wireless communication is over 63 dBc, and the responsivity of PD presents over 0.9 A/W for 20 samples of the total 23 PD. The total insertion loss reduces about 0.4${\~}$0.7 dB due to the integrated assembly of CWDM and PD.

  • PDF

Design of Printed Circuit Board for Clock Noise Suppression in T-DMB RF Receiver (지상파 DMB RF 수신기에서 클락 잡음 제거를 위한 인쇄 회로 기판 설계)

  • Kim, Hyun;Kwon, Sun-Young;Shin, Hyun-Chol
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.20 no.11
    • /
    • pp.1130-1137
    • /
    • 2009
  • This paper proposes a new clock routing design for suppressing clock harmonic effects in a Printed Circuit Board (PCB) for a terrestrial Digital Multimedia Broadcasting(DMB) system. Typical crystal reference frequencies that are widely used in DMB tuners are 16.384 MHz, 19.2 MHz, 24.576 MHz. When the high-order harmonic components of these reference frequencies fall near the RF channel frequencies, receiver sensitivity of the tuners is seriously degraded. In this work, we propose a new clock routing design in order to address the clock harmonic coupling issue. The proposed design incorporates two inductors for isolating the clock ground from the main ground, and adopts a new strip line-style routing instead of the conventional microstrip line style routing to minimize the overlap area with the main ground. As a result, the RF sensitivity of the T-DMB tuner is improved by 2 dB.

Verification of Nonlinear Numerical Analysis for Seismic Response of Single Degree of Freedom Structure with Shallow Foundation (비선형 수치해석을 통한 단자유도 얕은기초 구조물의 지진 응답특성 검증)

  • Choo, Yun-Wook;Lee, Jin-Sun;Kim, Dong-Soo
    • Journal of the Korean Geotechnical Society
    • /
    • v.29 no.3
    • /
    • pp.29-40
    • /
    • 2013
  • Seismic response of single degree of freedom system supported by shallow foundation was analyzed by using nonlinear explicit finite difference element code. Numerical analysis results were verified with dynamic centrifuge test results of the same soil profile and structural dimensions with the numerical analysis model at a centrifugal acceleration of 20 g. Differences between the analysis and the test results induced by the boundary conditions of control points can be reduced by adding additional local damping to the natural born cyclic hysteretic damping of the soil strata. The analysis results show good agreement with the test results in terms of both time histories and response spectra. Thus, it can be concluded that the nonlinear explicit finite difference element code will be a useful technique for estimating seismic residual displacement, earthpressure etc. which are difficult to measure during laboratory tests and real earthquake.

Risk Factors of Electrical Fire at the Panelboard and Investigation of Field Conditions (분전반에서의 전기화재 위험요소 및 현장실태조사 분석)

  • Kim, Hyang-Kon;Kim, Dong-Woo;Lee, Ki-Yeon;Choi, Yong-Sung;Choi, Chung-Seog;Choi, Hyo-Sang
    • Proceedings of the KIEE Conference
    • /
    • 2008.07a
    • /
    • pp.2206-2207
    • /
    • 2008
  • 본 논문에서는 분전반에서의 화재 위험 요소와 화재위험 요소에 대한 현장 실태조사 결과를 분석하였다. 분전반에서의 화재 위험 요소는 크게 전기적 요인, 환경적 요인, 물리적 요인으로 나눌 수 있으며 전기적 요인으로는 단락, 과부하(과전류), 접촉불량, 전류 불평형 등이 있으며 환경적 요인으로는 수분(염분 등), 먼지(분진, 목분, 철분 등), 온도(고온) 등에 의한 절연파괴, 기기 손상, 오동작 등이 있다. 물리적 요인으로는 기계적인 진동이나 충격 등에 의한 전기적 접속부의 이완에 의한 발열 등을 들 수 있다. 이러한 화재 위험 요인에 대하여 현장실태조사를 실시한 결과, 일부 분전반에서 내부에 먼지 등 이물질이 차단기, 전선, 단자대 등의 표면에 부착되어 있음을 확인할 수 있었으며 수분이나 염분 등의 영향으로 전극간 절연물 표면의 열화로 화재가 발생할 가능성이 있다. 또한, 적외선 열화상 분석결과, 일부 차단기 단자에서 국부 발열이 관측되었으며, 부하 분담의 불평형에 의한 발열도 확인되었다. 이러한 위험요인에 의한 화재 예방을 위하여 규정된 전선 굵기의 사용과 적정 체결압력의 확보, 상간 전류 불평형을 줄이기 위한 부하 분담의 조정이 필요하다. 향후, 분전반에서의 전기화재, 감전사고 등 전기재해의 예방을 위하여 지속적이고 체계적인 유지관리는 물론 사고 발생 전에 이상 징후를 사전에 감지하여 조치를 취할 수 있도록 하는 기술의 개발과 현장 적용이 요구된다.

  • PDF