• 전기의세계
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• v.28 no.6
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• pp.3-10
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• 1979

여기서는 마이크로컴퓨터의 시험법에 관해서 현재시판되고 있는 시험기와 함께 소개하고 단일 칩마이크로컴퓨터에 관해서 실시하고 있는 시험 패턴 설계예를 약간 상세히 기술한다. 또 마이크로컴퓨터용 LSI의 고장모우드, 고장메카니즘의 분류및 고장율, 신뢰성의 현장과 문제점에 관해서 기술함과 동시에 초기불량을 제거하여 신뢰성을 향상시키는 수단으로서의 스크리닝(screening)및 신뢰도예측에 관해서 소개하고 현장에 있어서의 문제점과 대책에 관해서 논의한다.

• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.101-107
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• 2005

This paper presents an one-chip controller for an electronic dispenser. The electronic dispenser is composed of electronic part and mechanical part. The electronic part is consisted of input keypad, micro-controller, display module, and pump module. In this paper we designed micro-controller for the electronic part. The micro-controller controls display module and pump module. The display module is composed by LCD device, and the pump module is composed by motor device . The micro-controller for an electronic dispenser is designed by VHDL. We used WX12864AP1 for the LCD device and SPS20 for the stepping motor. Also, the micro-controller is designed by Altera Quartus tool and verified with Agent 2000 Design-kit using APEX20K Device. In this paper, we present possibility to adopt of the biomedical device through the one-chip controller for the electronic dispenser.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.37-43
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• 2009

This paper describes a monolithic Darlington-cascade amplifier (DCA) operating at X-band, realized with a 0.35-micron SiGe bipolar process, which provides 45 GHz $f_T$. A conventional cascade amplifier was also designed on the same process and tested to establish a reference. Compared to the reference cascade amplifier, the proposed monolithic amplifier circuit exhibits an improved gain of 2.5 dB and improved output power 1-dB compression point of 5.2 dB with 72% wider bandwidth. Measurement results show 19.5 dB gain, 11.2 dBm 1-dB compression power, and 3.1 GHz bandwidth. These results demonstrate that the Darlington-cascade cell is an advantageous substitute to the conventional cascade amplifier.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.768-772
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• 2008

Today's microprocessor normally includes several processing cores to reduce the energy consumption without losing performance. In this paper, data transfer ordering mechanism can be efficiently used for cache coherence solution in unidirectional ring interconnect. RING-DATA ORDER combines the simplicity of GREEDY-ORDER and the performance of RING-ORDER. RING-DATA ORDER can be easily applicable to multicore processor with unidirectional ring interconnect.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.1-10
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• 2001

In this paper, a multistage parallel interference canceller (MPIC) and a partial multistage parallel interference canceller (PMPIC) are employed as a technique for improving the performance of the asynchronous DS-CDMA systems. The degree of the effect of the timing errors and phase errors on the interference cancellation capability of two types of cancellers is theoretically analyzed and the computer simulation is performed to confirm the analytical results. From the results, the large performance improvement is obtained by employing MPIC and PMPIC with perfect synchronization over the conventional matched filter, and the performance improvement obtained by MPIC and PMPIC is very close to each other as the number of the stage of MPIC and PMPIC increases. When the timing errors and phase errors are considered (in the case of imperfect synchronization), the performance improvement reduces as the performance degradation at the first stage (no cancellation) has a bad effect on the decision statistics at each stage. However MPIC and PMPIC have the strong interference cancellation capability in spite of imperfect synchronization as the number of the stage increases. An interference canceller, which has the strong interference cancellation capability as well as lower complexity for the implementation, is needed for practical systems with timing errors and phase errors because the perfect synchronization is impossible. Therefore, the excellent tradeoff between complexity and performance offered by PMPIC makes it an attractive approach for practical systems.

• Journal of Biomedical Engineering Research
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• v.18 no.4
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• pp.467-476
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• 1997

This paper presents a designing of a digital hearing aid processor (DHAP) chip being operated by a dedicated DSP core. The DHAP for hearing aid devices must be feasible within a size and power consumption required. Furthermore, it should be able to compensate for wide range of hearing losses and allow sufficient flexibility for the algorithm development. In this paper, a programmable 16-bit fixed-point DSP core is employed thor the designing of the DHAP. The designed DHAP performs a nonlinear loudness correction of 8 frequency bands based on audiometric measurements of impaired subjects. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has low-power feature and $5, 500\times5000$$\mu$$m^2$ dimensions that fit for wearable hearing aids.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3075-3077
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• 2000

이동통신단말기 등의 표시소자로 사용되는 LCD(Liquid Crystal Diode)나 LED(Light Emitting Diode)의 표현의 한계를 극복하고 보다 많은 정보를 표시할 수 있는 가상의 화면을 구성하기 위한 400dpi급 LED array 칩과 이를 구동하기 위한 driver 칩을 패키징하는 방법에 대하여 연구하였다. 연성 인쇄회로기판(flexible Printed Circuit) 기판 위에 칩을 실장하여 제품의 소형화와 경량화 그리고 전선을 대체하여 신뢰성을 높일 수 있도록 설계하였고 알루미늄 wire bonding법으로 각각의 칩을 연결하는데 있어 고려해야할 패키지의 조건에 대하여 연구하였다. 본 연구의 목적은 휴대용 이동통신단말기의 경박단 소화를 위한 패키징 기술을 확보하는데 있다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2006.05a
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• pp.119-123
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• 2006

본 논문에서는 마이크로프로세서의 기능을 수행하는 데 필수적이며 사용빈도가 높은 총 64개의 명령어를 정의한 후 이를 처리할 데이터패스를 구성해 스테이트 머쉰으로 제어하는 방식으로 실용적 8비트 마이크로프로세서를 VHDL로 설계를 하고 FPGA로 구현했다. 통상 마이크로프로세서 관련 논문에서는 기능적 시뮬레이션까지만 했거나, 인터럽트 기능이 없든지, 하드웨어로 구현을 하지 않았거나, 또는 개발 관련 내용이 자세히 제시되지 않았었다. 본 논문에서는 데이터 이동, 논리, 가산 연산뿐만 아니라 분기, 점프 연산도 실행할 수 있도록 해 연산 및 제어용도에 적합하도록 하였고, 스택, 외부 인터럽트 기능까지도 지원하도록 해 그 자체로서 완전한 실용적 마이크로프로세서가 되도록 하였다. 또한 프로그램 ROM까지도 칩 안에 넣어 전체 마이크로프로세서를 단일 칩으로 구현하였다. 타이밍 시뮬레이션으로 검증 후 제작 과정을 통해, 설계된 마이크로프로세서가 정상적으로 동작함을 확인하였다. Altera MAX+.PLUS II 통합개발환경 하에서 EP1K50TC144-3 FPGA 칩으로 구현을 하였고 최대 동작주파수는 9.39MHz까지 가능했고 사용한 로직 엘리먼트의 개수는 2813개로서 논리 사용률은 97%이었다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.163-168
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• 2018

We developed W-band transceiver module using open MMIC chip such as receiver single chip and transmitting power amplifier. In order to calculate the noise figure and output power value, we analyzed the W-band transition loss from the antenna to MMIC connection and constructed the 12 channel receiver and the 5 channel transmitter. And compared with the results of the measurement. As a result, the output power of the transmitter was similar to the analytical results and the measured results at room temperature and environmental conditions. The noise figure of the receiver was also similar, but some channels showed error of about 3 dB due to manufacturing error.