• The Magazine of the IEIE
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• v.1 no.2
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• pp.16-18
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• 1974

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.60-62
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• 1999

미세 회로 기술의 발전은 단일 칩에 집적될 수 있는 트랜지스터의 수를 지속적으로 증가시키고 있으며 이에 따라 설계의 복잡도 역시 크게 증가하고 있다. 이러한 설계 복잡도의 증가는 여러 기능 블록이 IP(Intellectual Property) 형태로 독립적으로 설계되어서 이들의 조합으로 새로운 시스템을 구성하는 시스템 온 칩(System On a Chi)과 같은 새로운 시스템 설계 방법에 대한 요구를 증가시키고 있다.[1]. 이런 시스템 온 칩에 사용될 메모리 시스템 역시 기존의 표준화된 메인 메모리 이 외에 각각의 다양한 응용에 적합한 맞춤형(Application Specific Standard Products) 내장 메모리 시스템 구조에 대한 필요성이 대두되고 있다. 이와 같이 특정 응용에 적합한 메모리 시스템을 설계할 수 있는 기본 정보를 제공해 주는 것이 필수적이다. 또한 이러한 정보에 따라 설계된 메모리 시스템에 대한 성능 평가할 환경도 함께 요구된다. 본 연구에서는 다양한 응용의 메모리 참조 특성을 분석하고 특성화하기 위하여 캐쉬 파라메터의 변화에 따른 캐쉬 접근 실패의 분포, 메모리 접근 영역의 분포, 참조 사이에 있는 유일한 참조의 수의 분포 등 다양한 정보를 제공해 주는 환경을 구축하였다.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2812-2814
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• 1999

그레이 영상 입출력이 가능하고, 다양한 영상 크기에 적용 가능한 아날로그 셀룰라 신경회로망을 설계하였다. 아날로그 셀룰라 신경회로망은 실시간 병렬처리가 가능하므로, 영상처리 패턴인식과 같은 분야에 유용하게 사용될 수 있다. 기존의 하드웨어로 구현된 셀를라 신경회로망은 이진 영상를 출력하고, 단일 칩에 구현할 수 있는 셀의 수에 제한이 있기 때문에 범용의 영상처리에 응용하기에 적합지 않다. 본 연구에서 설계된 셀룰라 신경회로망은 영상 입력 크기의 분해능을 향상시켜 그레이 영상 처리가 가능한 칩을 설계하였다. 설계된 셀룰라 신경회로망를 이용한 그레이 영상의 에지추출 시뮬레이션 결과, 선명한 에지 영상을 얻을 수 있었다

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.103-113
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• 2001

This paper described a design and implementation of a single-chip encoder/decoder using the LZSS algorithm and entropy coding in 0.6${\mu}{\textrm}{m}$ CMOS technology. Dictionary storage for the dictionary search processor(DISP) used a 2K$\times$8bit on-chip memory with 50MHz clock speed. It performs compression on byte-oriented input data at a data rate of one byte per clock cycle except when one out of every 33 cycles is used to update the string window of dictionary. In result, the average compression ratio is 46% by applied entropy coding of the LZSS codeword output. This is to improved on the compression performance of 7% much more then LZSS.

• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.55-62
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• 2019

The needs for small size and low power consumption of information devices is being implemented with SOC technology that implements the program on a single chip in Internet of Thing. Copyright disputes due to piracy are increasing in semiconductor chips as well, arising from disputes in the chip implementation of the design house and chip implementation by the illegal use of the source code. However, since the final chip implementation is made in the design house, it is difficult to protect the copyright. In this paper, we deal with the analysis method for extracting similarity and the criteria for setting similarity judgment in the dispute of source code written in HDL language. Especially, the chip which is manufactured based on the same specification will be divided into the same configuration and the code type.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.179-182
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• 2000

BWLL용 Ka-Band MMIC 저잡음 증폭기 칩을 InGaAs/GaAs 0.15um Gate 길이의 p-HEMT 공정을 이용하여 개발하였다. 칩 크기 2.5$\times$1.5$\textrm{mm}^2$의 2단으로 설계된 칩의 On-wafer 측정 결과, 24～27 GHz BWLL 주파수 대역에서 최소 19$\pm$0.2dB 이득과 최대 1.7dB의 잡음 지수와 최소 13dB의 반사손실의 특성을 얻었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.1-8
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• 2004

This paper describes the design of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been designed in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3 metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$ and the estimated power dissipation is less than 900 ㎽ with a single 5 V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8B
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• pp.646-656
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• 2008

In this paper, we design and verify the MAC chip of the two-stage AWG-based WDM-PON which considers 128 ONUs and 32 wavelengths. Each wavelength with the capacity of 1Gbps is allocated to ONU for downstream transmission but each wavelength for upstream transmission can be shared by four ONUs. Therefore, MAC protocol is required to avoid the collision and use the network resource efficiently among ONUs which are sharing the same wavelength. To design a request/permit-based MAC protocol, we define a unit-chip module called sub-MAC. The WDM-PON with 128 ONUs can be implemented by using 32 sub-MAC modules. The sub-MAC consists of one control unit, one receipt unit and four transmission units. The state transition diagram of the module is described by the internal/external control signals among the functional units. The function of the sub-MAC module is verified through logic simulation using ModelSIM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6B
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• pp.456-468
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• 2008

In this paper, we design Input/Output modules as a preference work for implementation of hybrid two stage AWG based WDM-PON and verify operations of each function modules through the logic simulation. This WDM-PON system provides service to 128 ONUs through 32 wavelength and one wavelength is shared for upstream transmission with four ONU while each wavelength is allocated to each ONU for downstream transmission. The designed WDM-PON MAC chip is based on sub-MAC which consists of one control unit and reception unit and four transmission unit. To design the reception and transmission unit of sub-MAC, we define the functions of the sub-MAC, pins of the modules, control signal and timing of each signal. We intend to design MAC chip with 1Gbps transmission rate. Thus the designed MAC chip is worked on 125MHz clock rate. We define FSM and design Input/Output modules with VHDL. The logic simulation of the modules is executed by the ModelSIM simulator.