• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 추계학술대회 초록집
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• pp.43.1-43.1
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• 2010

In the crystalline silicon solar cells, the full area aluminum_back surface field(BSF) is routinely achieved through the screen-printing of aluminum paste and rapid firing. It is widely used in the industrial solar cell because of the simple and cost-effective process to suppress the overall recombination at the back surface. However, it still has limitations such as the relatively higher recombination rate and the low-to-moderate reflectance. In addition, it is difficult to apply it to thinner substrate due to wafer bowing. In the recent years, the dielectric back-passivated cell with local back contacts has been developed and implemented to overcome its disadvantages. Although it is successful to gain a lower value of surface recombination velocity(SRV), the series resistance($R_{series}$) becomes even more important than the conventional solar cell. That is, it is a trade off relationship between the SRV and the $R_{series}$ as a function of the contact size, the contact spacing and the geometry of the opening. Therefore it is essential to find the best compromise between them for the high efficiency solar cell. We have investigated the optimal design for the local back contact by using PC1D simulation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.81-81
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• 2009

반도체 산업의 중심 소재인 실리콘(Si)은 사용 목적과 환경에 따라 물성적 한계가 표출되기 시작했다. 그래서 각각의 목적에 맞는 재료의 개발이 필요하다는 것을 인식하게 되었다. SiC wafer는 큰 band gap energy와 고온 안정성, 캐리어의 높은 드리프트 속도 그리고 p-n 접합이 용이하다. 또한 소재 자체가 화학적으로 안정하고 $500\sim600^{\circ}C$에서 소자 제조 시 고온공정이 가능하며, 실리콘이나 GaAs에 비해 고출력을 낼 수 있는 재료이다. 반도체 소자로 이용하기 위한 wafer 가공 공정에 있어 물리적 힘에 의한 stress를 많이 받아 wafer가 휘는 현상이 생긴다. 반도체 소자의 기본이 되는 wafer가 휨 현상을 일으키면 wafer 위에 소자가 올라갈 경우 소자의 불균일성 때문에 반도체의 물성에 나쁜 영향을 미치게 된다. 그래서 반도체 소자의 기본이 되는 wafer의 휨 현상 개선이 중요하다. 본 연구에서는 산화로에서 Ar 분위기에서 압력 760torr, 온도 $1100^{\circ}C$ 부근에서의 조건으로 진행을 하여 wafer의 Flatness Tester(FT-900, NIDEK) 장비로 SORI, BOW, GBIR 값의 변화에 초점을 맞추었다. SiC 단결정을 sawing후 가공 전 wafer를 열처리하여 가공을 진행하는 것과 열처리 하지 않은 wafer의 SORI, BOW, GBIR 값 비교, 그리고 lapping, grinding, polishing 등의 가공 진행 중간 중간에 열처리를 하여 진행하는 것과 가공 진행 중간 중간에 열처리를 하지 않고 진행한 wafer의 SORI, BOW, GBIR 값의 비교를 통해 wafer의 휨 현상 개성에 관해 알아본다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2008년도 춘계학술대회 논문집
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• pp.390-393
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.365-365
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• 2010

In this paper, silicon nitride thin films with different silane and ammonia gas ratios were deposited and characterized for the antireflection and passivation layer of high efficiency single crystalline silicon solar cells. As the flow rate of the ammonia gas increased, the refractive index decreased and the band gap increased. Consequently, the transmittance increased due to the higher band gap and the decrease of the defect states which existed for the 1.68 and 1.80 eV in the SiNx films. The reduction in the carrier lifetime of the SiNx films deposited by using a higher $NH_3/SiH_4$ flow ratio was caused by the increase of the interface traps and the defect states in/on the interface between the SiNx and the silicon wafer. The silicon and nitrogen rich films are not suitable for generating both higher carrier lifetimes and transmittance. These results indicate that the band gap and the defect states of the SiNx films should be carefully controlled in order to obtain the maximum efficiency for c-Si solar cells.

• 한국정밀공학회지
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• 제21권10호
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• pp.26-33
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• 2004

Ultra precision grinding technology has been developed from the refinement of the abrasive, the development of high stiffness equipment and grinding skill. The conventional wafering process which consists of lapping, etching, 1 st, 2nd and 3rd polishing has been changed to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Furthermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focuses on the flatness of the ground wafer. Generally, the ground wafer has concave pronto because of the difference of wheel path density, grinding temperature and elastic deformation of the equipment. Wafer tilting is applied to avoid non-uniform material removal. Through the geometric analysis of wafer grinding process, the profile of the ground wafer is predicted by the development of profile simulator.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.98-101
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• 2003

As the ultra precision grinding can be applied to wafering process by the refinement of the abrasive. the development of high stiffness equipment and grinding skill, the conventional wafering process which consists of lapping, etching, 1st, 2nd and 3rd polishing could be exchanged to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Futhermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focused on the flatness of the ground wafer. Generally, the ground wafer has concave profile because of the difference of wheel path density, grinding temperature and elastic deformation of the equiptment. Tilting mathod is applied to avoid such non-uniform material removes. So, in this paper, the geometric analysis on grinding process is carried out, and then, we can predict the profile of th ground wafer by using profile simulation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.85-88
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• 2004

Mono-crystalline silicon(mono-Si) is both abundant in our environment and an excellent material for Si device applications. However, single crystalline silicon solar cell has been considered to be expensive for terrestrial applications. For that reason, the last few years have seen very rapid progress in the research and development activities of layer transfer(LT) processes. Thin film Si layers which can be detached from a reusable mono-Si wafers served as a substrate for epitaxial growth. The epitaxial films have a very high efficiency potential. LT technology is a promising approach to reduce fabrication cost with high efficiency at large scale since expensive Si substrate can be recycled. Low quality Si can be used as a substrate. Therefore, we propose one of the major technologies on fabricating thin film Si substrate using a LT. In this paper, we study the LT method using the electrochemical etching(ECE) and solid edge.

• 전자공학회논문지A
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• 제32A권2호
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• pp.66-72
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• 1995

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.136-137
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• 2008

태양전지의 효율은 실리콘 자체의 특성에 의해서 결정 되거나 완성된 실리콘을 통해 태양전지를 제조하는 과정에서 Texturing, Coating 등을 통해 효율을 변화 시킬 수 있다. PC1D를 이용해 Texturing, Base Resistivity, Emitter Doping등을 조절해가며 고효율 태양전지를 위한 시뮬레이션을 하였다. Texture Angle이 $80^{\circ}$, Texture Depth가 2um, Base Resistivity가 0.2[${\Omega}{\cdot}cm$], Emitter Doping이 8*Exp(19)[$cm^{-3}$]일 경우 효율이 19.9%로 최적화 되었다.

• 한국결정성장학회지
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• 제28권4호
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• pp.141-147
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• 2018

태양광 에너지는 깨끗하며 무한한 재생에너지의 한가지로 많은 관심을 받아왔다. 태양광 에너지는 다결정 실리콘 웨이퍼 혹은 단결정 실리콘 웨이퍼로 구성된 솔라셀에 의해서 전기에너지로 전환된다. 제조원가를 낮추기 위하여 한 개의 석영 도가니에 폴리실리콘의 충진 크기를 증가시키는 연구가 많이 개발되어 왔다. 충진 크기를 증가시키면, 쵸크랄스키 공정장비의 온도제어가 강한 멜트 대류 때문에 힘들어진다. 본 연구에서는 20 inch와 24 inch 석영도가니와 90 Kg, 120 Kg, 150 Kg, 200 Kg, 250 Kg의 다양한 폴리실리콘 충진 크기에서 시뮬레이션을 통해 장비 온도 프로파일을 얻었으며, 실제값과 비교하고 분석하였다. 시뮬레이션 온도 프로파일과 실제 온도프로파일이 잘 일치하였으며, 이로써 충진 사이즈가 증가할 경우, 실제온도 프로파일 최적화를 위해 시뮬레이션을 사용할 수 있게 되었다.