• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.519-524
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• 2002

In this paper we study the qualify of sequential coverage analysis under a scenario of distributed stochastic simulation known as MRIP(Multiple Replications In Parallel) in terms of the confidence intervals of coverage and the speedup. The estimator based in the F-distribution was applied to the sequential coverage analysis of steady-state means. in simulations of the $M/M/1/{\infty},\;M/D/I/{\infty}\;and\;M/H_{2}/1/{\infty}$ queueing systems on a single processor and multiple processors. By using multiple processors under the MRIP scenario, the time for collecting many replications needed in sequential coverage analysis is reduced. One can also easily collect more replications by executing it in distributed computers or clusters linked by a local area network.

• Journal of Digital Contents Society
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• v.8 no.3
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• pp.279-288
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• 2007

Recently, Baruah et. al. proposed an optimal Pfair scheduling algorithm in the real-time multiprocessor system environments, and several variants of it were presented. All these algorithms assume the fixed unit quantum size. However, under Pfair based scheduling algorithms that are global scheduling technique, quantum size has direct influence on the scheduling overheads such as task switching and cache reload. We proposed a method for deciding the optimal quantum size[2] and an improved method for the task set whose utilization e is less than or equal to $e\;{\leq}\;p/3+1$[3]. However, these methods use repetitive computation of the task's utilization to determine the optimal quantum size. In this paper, we propose a more efficient method that can determine the optimal quantum size in constant time.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.149-159
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• 2000

In this paper, we propose a new class of MIN (Multistage Interconnection Network) called SCMIN(ShortCut MIN) which can form a cheap and efficient packet switching interconnection network. SCMIN satisfies full access capability(FAC) and has multiple redundant paths between processor-memory pairs even though SCMIN is constructed with 2.5N-4 SEs which is far fewer SEs than that of MINs. SCMIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. Therefore, SCMIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.169-174
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• 1986

This thesis investigates the scanning time ; one of the most important performance index of Programmable Controller(PC). The multiprocessor architecture of the large PC considered in this thesis are classified as architecture 1 and architecture 2 by the bus control methods. The queuing model of each architecture is developed. Form the analysis it is observed that in the case of the number of processors less than 3 the best architecture of the large PC is the architecture 2 and in the case of the number of processors greater than 2 the best architecture of the large PC is the architecture 1.

• The KIPS Transactions:PartD
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• v.15D no.3
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• pp.355-360
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• 2008

The complicated embedded system for multi-tasking requires RTOS(real-time operating system). It uses the optimal OS and processor to each embedded system on the heterogeneous development environment. This paper is proposed to use UML profile of OS API and Processor Configuration, instead of cross-compiling for developing the heterogeneous embedded system. This reduces the development time and cost through generating the automatic source code with the profile information of each embedded system. We generate and port the code after modeling the two heterogeneous real time operating systems (brickOS and uC/OS-II) and the processors (Hitachi H8 and Intel PXA255) with our proposed profile of the heterogeneous embedded system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3C
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• pp.175-182
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• 2011

This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.53-62
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• 2010

Recently, various industrial embedded systems including vehicles controlled electronically are evolving to distributed multi-micro controller system. Accordingly, there is a need for standard CAN(Controller Area Network) protocol that ensures high stability and reliability of communication and is simple to construct object-oriented system with high control efficiency. CAN communication interface used general-purpose processor doesn't have many limitations in various application development because of fixed hardware architecture. This paper design and implement a CAN communication interface system based on FPGA. It is verified function and performance of system through monitoring communication with existing AT90CAN128 controller. Implemented CAN communication interface can be reused in development of application systems based on FPGA. And it provides low-cost, small-size and low-power design advantages.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.3
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• pp.217-227
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• 1989

A process control graphic system is proposed as an efficient tool for monitoring the operation of power plant. It uses the multi-processor structure with 60 Kbyte shared memory as an implemental type of the distributed computer system, so that it is flexible, functionally extensible, and applicable to real-time process. The shared memory is used as a real-time database handling the process values and operator's commands. The database files, generated by the user-interactive graphic editor developed for the system or text editor, have the characteristics of simplicity and user-friendliness. The process control graphic system, that can monitor the operation of boiler and function as a backup controller in case of failure in boiler controller, is applied to Ulsan power plant. As a result, it displays the operating data of the boiler process without error by 14 pages of color graphic image according to the operation menu, and additionally functions well as a fault-tolerant control system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1659-1666
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• 2010

The High maneuver missiles use various interfaces and high speed guidance and control loop. Hardware-in-the-Loop(HWIL) simulation control system, therefore, should have high performance computing power and hardware interface capabilities, and should be developed using IT technology with which real time operating system, embedded system, data communication technology, and real time hardware control are integrated. This paper suggests the control system design techniques, such as a system hardware configuration, a job distribution algorithm for high performance multi-processors, a real time calculation and control mechanism, inter-processor communication mechanism, and a real time data acquisition technique, to perform the HWIL simulation for high maneuver missile system.

• The KIPS Transactions:PartA
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• v.8A no.1
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• pp.9-15
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• 2001

영상에 관련된 다양한 응용 시스템들을 구현하는 많은 연구들이 진행되어 왔지만, 그러한 영상 관련 응용 시스템을 구현함에 있어서 처리속도의 저하로 인하여 많은 어려움을 겪고 있다. 이를 해결하기 위해 대두된 여러 방법들 중에서 최근 하드웨어 접근 방법에 고려한 많은 관심과 연구가 진행되고 있다. 본 논문은 영상을 실시간으로 처리하기 위하여 하드웨어 구조를 갖는 병렬처리시스템을 기술하며, 또한 병렬처리시스템을 얼굴 검색 시스템에 적용한 후 처리속도 및 실험 결과를 기술한다. 병렬처리시스템은 SIMD와 MIMD가 결합된 구조를 갖고 있기 때문에 다양한 영상 응용시스템에 대해서 융통성과 효율성을 제공하며, 144개의 처리기와 12개의 다중접근기억장치, 외부 메모리 모듈을 위한 인터페이스와 외부 프로세서 장치(i960Kx)와의 통신을 위한 인터페이스로 구성되어있다. 다중접근기억장치는 메모리 모듈선택회로, 데이터 라이팅회로, 그리고, 주소계산 및 라우팅회로로 구성되어 있다. 또한 얼굴 검색 시스템을 병렬처리 시스템에 적합한 병렬화를 제공하기 위해 메쉬방법을 이용하여 전처리, 정규화, 4개 특징값 추출, 그리고 분류화로 구성하였다. 병렬처리시스템은 하드웨어 모의실험 패키지인 CADENCE사의 Verilog-XL로 모의실험을 수행하여 기능과 성능을 검증하였다.