• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.123-127
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• 2021

Millimeter-wave tracking radars should be operated in various environmental restrictions, thus they demand more computing power and smaller size compared to conventional tracking radars. This paper presents the design and implementation of the compact power supply for millimeter-wave tracking radar applications. To meet requirements of low voltage/high current and voltage accuracy for FPGA/DSP digital circuits, Point of Load (POL) converters are used in order to enhance power density and system efficiency. LDO (Low Dropout) is applied for the output voltage under the light load condition, then the single-input-multi-output power supply with max power of 375 W and 8 outputs is developed. The proposed power supply achieves output voltage accuracy of ±2 % and noise level of <50 mVpp % under full load conditions.

• Korean Journal of Optics and Photonics
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• v.33 no.3
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• pp.106-112
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• 2022

A two-dimensional optical code division multiple access (OCDMA) encoder/decoder, which is composed of add/drop filters and all-pass filters for delay operation, is proposed. An example design is presented, and its feasibility is illustrated through numerical simulations. The chip area of the proposed OCDMA encoder/decoder could be about one-third that of a previous OCDMA device employing delay waveguides. Its performance is numerically investigated using the transfer-matrix method combined with the fast Fourier transform. The autocorrelation peak level over the maximum cross-correlation level for incorrect wavelength hopping and spectral phase code combinations is greater than 3 at the center of the correctly decoded pulse, which assures a bit error rate lower than 10^-3, corresponding to the forward error-correction limit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1210-1230
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• 1997

In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.

• Journal of Broadcast Engineering
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• v.22 no.4
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• pp.484-495
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• 2017

The development of display devices and the increase of network transmission bandwidth bring demands for over 2K high resolution video such as panorama video, 4K ultra-high definition commercial broadcasting, and ultra-wide viewing video. To compress these image sequences with significant amount of data, High Efficiency Video Coding (HEVC) standard with the highest coding efficiency is a promising solution. HEVC, the latest video coding standard, provides high encoding efficiency using various advanced encoding tools, but it also requires significant amounts of computation complexity compared to previous coding standards. In particular, the complexity of HEVC decoding process is a imposing challenges on real-time playback of ultra-high resolution video. To accelerate the HEVC decoding process for ultra high resolution video, this paper introduces a data-level parallel video decoding method using slice and/or tile supported by HEVC. Moreover, deblocking filter process is further parallelized. The proposed method distributes independent decoding operations of each tile and/or each slice to multiple threads as well as deblocking filter operations. The experimental results show that the proposed method facilitates executions up to 2.0 times faster than the HEVC reference software for 4K videos.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.2
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• pp.1-9
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• 2008

As the security requirements of mobile phones have been increasing, there have been extensive researches using one biometric feature (e.g., an iris, a fingerprint, or a face image) for authentication. Due to the limitation of uni-modal biometrics, we propose a method that combines face and iris images in order to improve accuracy in mobile environments. This paper presents four advantages and contributions over previous research. First, in order to capture both face and iris image at fast speed and simultaneously, we use a built-in conventional mega pixel camera in mobile phone, which is revised to capture the NIR (Near-InfraRed) face and iris image. Second, in order to increase the authentication accuracy of face and iris, we propose a score level fusion method based on SVM (Support Vector Machine). Third, to reduce the classification complexities of SVM and intra-variation of face and iris data, we normalize the input face and iris data, respectively. For face, a NIR illuminator and NIR passing filter on camera are used to reduce the illumination variance caused by environmental visible lighting and the consequent saturated region in face by the NIR illuminator is normalized by low processing logarithmic algorithm considering mobile phone. For iris, image transform into polar coordinate and iris code shifting are used for obtaining robust identification accuracy irrespective of image capturing condition. Fourth, to increase the processing speed on mobile phone, we use integer based face and iris authentication algorithms. Experimental results were tested with face and iris images by mega-pixel camera of mobile phone. It showed that the authentication accuracy using SVM was better than those of uni-modal (face or iris), SUM, MAX, NIN and weighted SUM rules.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• Science of Emotion and Sensibility
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• v.14 no.3
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• pp.347-360
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• 2011

To find out characteristics of TV home shopping's virtual space deepness styling, this study had analysis characteristics of space deepness which is showed on flat TV screen with actually aired 6 dinnerware sales case, at $C^*$ home shopping, March.2005~November.2010, and survey consumer's emotional verbal image according to space styling character to get space deepness, which were shown on flat TV screen with camera angle, and research mutual relation with consumer preference. Also consumer's typical emotional verbal images for each space styling images for brand dinner ware sales had been extracted with reliability analysis, factor analysis, and multi dimensional scaling MDS using SPSS. Styling characteristics of space deepness were contrast of size, layering, vertical arrangement, and perspective arrangement, and used camera angles were bird's eye view, hi angle, and eye level. Result from the research is, highly marked consumer preferred styling material had a deep corelation to material's main factor and perceived emotional verbal images. Therefore this research could bring forward to new consumer preferred styling characteristics according to camera angle. Furthermore, it will be possible to make a study of preferred styling material through evaluation of quantitative spectators of in this area.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.425-434
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• 2007

Even though Internet backbone speeds have increased in the last few years due to projects like Internet 2 and NGI, many high performance distributed applications are able to achieve only a small fraction of the available bandwidth. The cause of such problem is due to a character of TCP/IP. The primary goal of this protocol is reliable data transmission. Therefore high speed data transmission didn't be considered when TCP/IP is designed. Hence several researchers have been studied in order to solve the problem of TCP/IP. One of these research results, parallel transfer technique, solves this problem to use parallel TCP connections on application level. Additionally, this technique is compatibility. Recently, these researchers have been studied a mechanism to decide the number of parallel TCP connections. However, some researchers reported the number of parallel TCP connection base on only empirical results. Although hardware performance of host affects transmission rate, the hardware performance didn't be considered in their works. Hence, we collect all data related to transmission rate, such as hardware state information (cpu utilization, interrupt, context switch). Then, we analyzed collected data. And, we suggest a new mechanism determining number of parallel TCP connections for maximization of performance based on our analysis.

• The KIPS Transactions:PartA
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• v.18A no.4
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• pp.135-142
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• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.44-51
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• 2000

We have analyzed optical matched filters considering the third order signals in the optical code division multiple access (CDMA) system based on optical series coupler access encoder (SCAE) and series coupler access decoder (SCAD). In previous studies, the performance evaluation of the optical CDMA system using SCAE and SCAD was not sufficiently accurate because they analyzed system performance only considering the first order signals. Since optical SCAE and SCAD intrinsically have high order signals of various patterns as the number of coupler increases, they change auto- and cross-correlation intensities. Thus, it is necessary to investigate properties of the third order signals so that we may analyze the exact performance of system. In this paper, we mathematically interpret the optical signals up to the third order, and analyzed the effects of th third order signals on auto- and cross-correlation intensities. In result, as ${\alpha}$(coupling coefficient) value increases, the intensity of the third order signals increases. It is found that the peak to side-lobe ratio considering the third order signals is degraded by 3.75 dB at N(coupler number)=5 and ${\alpha}$=0.5. Also if threshold value in receiver is set by main-lobe peak of the first order signals, it is found that the number of users in an optical CDMA system is limited because the intensity peak of side-lobes is raised by the third order signals.