• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.06a
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• pp.213-214
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• 2017

홀로그램을 생성하기 위해서 많은 양의 계산을 필요하기 때문에 고속 홀로그램 생성 방법이 필요하다. 본 논문에서는 다중 프로세서와 다중 GPGPU의 스케줄링을 이용하여 고속화 하는 방법을 제안하고 구현하였다. 다중 프로세서를 이용하여 입력과 출력부분을 나누어 동기화 동작을 줄이고, 버퍼를 이용하여 커널과 커널 사이의 대기 시간을 줄일 수 있도록 스케줄링 하였다. nVidia사의 GTX680(Kepler구조) 2개를 이용하여 구현하였을 때, 이전 연구에서 제안한 방법에 비하여 약 70% 정도 계산시간을 줄일 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.07a
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• pp.563-566
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• 2020

본 논문은 초고해상도 컴퓨터 홀로그램 생성을 위한 GPU 기반 2D Shift-FFT 의 효율적인 구현 방법을 제안한다. 본 연구가 제안하는 알고리즘은 기존에 여섯 단계로 이루어진 처리과정을 다섯 단계로 줄임으로서, 병렬처리에서 비효율적인 메모리 접근 과정을 줄인다. 또한, 핀드(pinned) 메모리 기반의 CPU-GPU 데이터 통신 통로인 핀드 버퍼(pinned buffer)를 사용하고 다중 스트림을 채용함으로써, GPU 활용의 주요 병목원인이 되는 데이터 통신의 부하를 줄이고 GPU 활용 효율을 높인다. 본 연구는 제안하는 알고리즘의 효용성을 증명하기 위해 서로 다른 두 시스템에 알고리즘을 구현하고, 다양한 크기의 행렬에 대한 2D-FFT 처리에 대한 성능을 측정하였다. 그 결과, CPU 기반의 FFTW 라이브러리 대비 최대 3 배, 동일한 GPU 를 사용하는 cuFFT 라이브러리 대비 최대 1.5 배 높은 성능을 달성하였다. 이러한 결과는, 본 연구가 제안하는 알고리즘의 효용성을 보여주는 결과다.

• Journal of KIISE
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• v.43 no.4
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• pp.399-403
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• 2016

Deferred Shading is a shading technique that postprocesses pixels in the screen space, following geometry-only rendering passes with depth buffering. Unlike typical shadow mapping techniques, this technique allows us to render shadows from multiple light sources without changing the structure of the rendering pipelines. This paper presents a deferred shadow mapping technique and its extension to soft shadows using mipmapping. Our technique first generates visibility maps from light sources, and blurs the visibility maps for deferred shading. This strategy leads to efficient soft-edged shadows, but does not incorporate depth variation, producing light bleeding to some extent. In order to suppress the light-bleeding artifacts, we also propose a depth-adaptive mipmap sampling technique in the screen space.

• Korean Journal of Environment and Ecology
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• v.31 no.2
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• pp.252-265
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• 2017

This study aims to analyze the landscape ecological characteristics of green spaces within built up area of high density and evaluate the potential applicability of green patches, thereby introducing urban garden for generating green networks in residence areas. To this end, Yeoksam-Dong was selected as the site area since it is classified as both green initiative zone and alienated area of park service in Seoul. First, the current condition of green spaces in Yeoksam-Dong was identified by five categories: Street trees, private garden, public pocket garden, rooftop garden, and park. Then, the landscape index analysis through FRAGSTATS and connectivity assessment via multi-buffer zone analysis were carried out for analyzing the green networks and evaluating the potential value of green space. The results showed that the degree to which green areas in the site were distributed is arranged in the order of street tree, private garden, public pocket garden, park, and rooftop garden. In case of the street trees whose total core area (TCA, $1,618m^2$) is as high as the park's ($1,128m^2$). Private garden has potential for green network in built up area of high density by gardening since the shape of the patches are irregular (ED = 78.1m/ha) and the average distance among the patches is close (ENN=33.9m). Public pocket garden has also potential for gardening according to the result that it was found to be distributed evenly (LPI=5.7%, SHEI=0.9) with exposing external disturbance ($TCA=66m^2$). For the green network, 84% of all the study site is covered by small green network in 50m butter range of connected green area. The effect of green network was expected through gardening in public pocket garden (27%) and street tree (26%). Accordingly, it is encouraged to actively utilize street tree, private gardens, and rooftop gardens and to establish the urban gardens like local-based community gardens in public pocket garden where a variety of activities can be carried out near residential areas. By doing so, green networks can effectively be established in built up area with high density. The results of this study can contribute positively to fostering the creation of various types of urban gardens.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.