• Title/Summary/Keyword: 뉴로모픽

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Performance Analysis of Speech Recognition Model based on Neuromorphic Architecture of Speech Data Preprocessing Technique (음성 데이터 전처리 기법에 따른 뉴로모픽 아키텍처 기반 음성 인식 모델의 성능 분석)

  • Cho, Jinsung;Kim, Bongjae
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.3
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    • pp.69-74
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    • 2022
  • SNN (Spiking Neural Network) operating in neuromorphic architecture was created by mimicking human neural networks. Neuromorphic computing based on neuromorphic architecture requires relatively lower power than typical deep learning techniques based on GPUs. For this reason, research to support various artificial intelligence models using neuromorphic architecture is actively taking place. This paper conducted a performance analysis of the speech recognition model based on neuromorphic architecture according to the speech data preprocessing technique. As a result of the experiment, it showed up to 84% of speech recognition accuracy performance when preprocessing speech data using the Fourier transform. Therefore, it was confirmed that the speech recognition service based on the neuromorphic architecture can be effectively utilized.

Application Scenario of Integrated Development Environment for Autonomous IoT Applications based on Neuromorphic Architecture (뉴로모픽 아키텍처 기반 자율형 IoT 응용 통합개발환경 응용 시나리오)

  • Park, Jisu;Kim, Seoyeon;Kim, Hoinam;Jeong, Jaehyeok;Kim, Kyeongsoo;Jung, Jinman;Yun, Young-Sun
    • Smart Media Journal
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    • v.11 no.2
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    • pp.63-69
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    • 2022
  • As the use of various IoT devices increases, the importance of IoT platforms is also rising. Recently, artificial intelligence technology is being combined with IoT devices, and research applying a neuromorphic architecture to IoT devices with low power is also increasing. In this paper, an application scenario is proposed based on NA-IDE (Neuromorphic Architecture-based autonomous IoT application integrated development environment) with IoT devices and FPGA devices in a GUI format. The proposed scenario connects a camera module to an IoT device, collects MNIST dataset images online, recognizes the collected images through a neuromorphic board, and displays the recognition results through a device module connected to other IoT devices. If the neuromorphic architecture is applied to many IoT devices and used for various application services, the autonomous IoT application integrated development environment based on the neuromorphic architecture is expected to emerge as a core technology leading the 4th industrial revolution.

NAAL: Software for controlling heterogeneous IoT devices based on neuromorphic architecture abstraction (NAAL: 뉴로모픽 아키텍처 추상화 기반 이기종 IoT 기기 제어용 소프트웨어)

  • Cho, Jinsung;Kim, Bongjae
    • Smart Media Journal
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    • v.11 no.3
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    • pp.18-25
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    • 2022
  • Neuromorphic computing generally shows significantly better power, area, and speed performance than neural network computation using CPU and GPU. These characteristics are suitable for resource-constrained IoT environments where energy consumption is important. However, there is a problem in that it is necessary to modify the source code for environment setting and application operation according to heterogeneous IoT devices that support neuromorphic computing. To solve these problems, NAAL was proposed and implemented in this paper. NAAL provides functions necessary for IoT device control and neuromorphic architecture abstraction and inference model operation in various heterogeneous IoT device environments based on common APIs of NAAL. NAAL has the advantage of enabling additional support for new heterogeneous IoT devices and neuromorphic architectures and computing devices in the future.

Feature Representation Method to Improve Image Classification Performance in FPGA Embedded Boards Based on Neuromorphic Architecture (뉴로모픽 구조 기반 FPGA 임베디드 보드에서 이미지 분류 성능 향상을 위한 특징 표현 방법 연구)

  • Jeong, Jae-Hyeok;Jung, Jinman;Yun, Young-Sun
    • Journal of Software Assessment and Valuation
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    • v.17 no.2
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    • pp.161-172
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    • 2021
  • Neuromorphic architecture is drawing attention as a next-generation computing that supports artificial intelligence technology with low energy. However, FPGA embedded boards based on Neuromorphic architecturehave limited resources due to size and power. In this paper, we compared and evaluated the image reduction method using the interpolation method that rescales the size without considering the feature points and the DCT (Discrete Cosine Transform) method that preserves the feature points as much as possible based on energy. The scaled images were compared and analyzed for accuracy through CNN (Convolutional Neural Networks) in a PC environment and in the Nengo framework of an FPGA embedded board.. As a result of the experiment, DCT based classification showed about 1.9% higher performance than that of interpolation representation in both CNN and FPGA nengo environments. Based on the experimental results, when the DCT method is used in a limited resource environment such as an embedded board, a lot of resources are allocated to the expression of neurons used for classification, and the recognition rate is expected to increase.

Convergence Study on Fabrication and Plasma Module Process Technology of ReRAM Device for Neuromorphic Based (뉴로모픽 기반의 저항 변화 메모리 소자 제작 및 플라즈마 모듈 적용 공정기술에 관한 융합 연구)

  • Kim, Geunho;Shin, Dongkyun;Lee, Dong-Ju;Kim, Eundo
    • Journal of the Korea Convergence Society
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    • v.11 no.10
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    • pp.1-7
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    • 2020
  • The manufacturing process of the resistive variable memory device, which is the based of neuromorphic device, maintained the continuity of vacuum process and applied plasma module suitable for the production of the ReRAM(resistive random access memory) and process technology for the neuromorphic computing, which ensures high integrated and high reliability. The ReRAM device of the oxide thin-film applied to the plasma module was fabricated, and research to improve the properties of the device was conducted through various experiments through changes in materials and process methods. ReRAM device based on TiO2/TiOx of oxide thin-film using plasma module was completed. Crystallinity measured by XRD rutile, HRS:LRS current value is 2.99 × 103 ratio or higher, driving voltage was measured using a semiconductor parameter, and it was confirmed that it can be driven at low voltage of 0.3 V or less. It was possible to fabricate a neuromorphic ReRAM device using oxygen gas in a previously developed plasma module, and TiOx thin-films were deposited to confirm performance.

QoS-Aware Optimal SNN Model Parameter Generation Method in Neuromorphic Environment (뉴로모픽 환경에서 QoS를 고려한 최적의 SNN 모델 파라미터 생성 기법)

  • Seoyeon Kim;Bongjae Kim;Jinman Jung
    • Smart Media Journal
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    • v.12 no.4
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    • pp.19-26
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    • 2023
  • IoT edge services utilizing neuromorphic hardware architectures are suitable for autonomous IoT applications as they perform intelligent processing on the device itself. However, spiking neural networks applied to neuromorphic hardware are difficult for IoT developers to comprehend due to their complex structures and various hyper-parameters. In this paper, we propose a method for generating spiking neural network (SNN) models that satisfy user performance requirements while considering the constraints of neuromorphic hardware. Our proposed method utilizes previously trained models from pre-processed data to find optimal SNN model parameters from profiling data. Comparing our method to a naive search method, both methods satisfy user requirements, but our proposed method shows better performance in terms of runtime. Additionally, even if the constraints of new hardware are not clearly known, the proposed method can provide high scalability by utilizing the profiled data of the hardware.

Development of a Simulator for RBF-Based Networks on Neuromorphic Chips (뉴로모픽 칩에서 운영되는 RBF 기반 네트워크 학습을 위한 시뮬레이터 개발)

  • Lee, Yeowool;Seo, Keyongeun;Choi, Daewoong;Ko, Jaejin;Lee, Sangyub;Lee, Jaekyu;Cho, Heyonjoong
    • KIPS Transactions on Computer and Communication Systems
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    • v.8 no.11
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    • pp.251-262
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    • 2019
  • In this paper, we propose a simulator that provides various algorithms of RBF networks on neuromorphic chips. To develop algorithms based on neuromorphic chips, the disadvantages of using simulators are that it is difficult to test various types of algorithms, although time is fast. This proposed simulator can simulate four times more types of network architecture than existing simulators, and it provides an additional a two-layer structure algorithm in particular, unlike RBF networks provided by existing simulators. This two-layer architecture algorithm is configured to be utilized for multiple input data and compared to the existing RBF for performance analysis and validation of utilization. The analysis showed that the two-layer structure algorithm was more accurate than the existing RBF networks.

Implementation of Encoder/Decoder to Support SNN Model in an IoT Integrated Development Environment based on Neuromorphic Architecture (뉴로모픽 구조 기반 IoT 통합 개발환경에서 SNN 모델을 지원하기 위한 인코더/디코더 구현)

  • Kim, Hoinam;Yun, Young-Sun
    • Journal of Software Assessment and Valuation
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    • v.17 no.2
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    • pp.47-57
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    • 2021
  • Neuromorphic technology is proposed to complement the shortcomings of existing artificial intelligence technology by mimicking the human brain structure and computational process with hardware. NA-IDE has also been proposed for developing neuromorphic hardware-based IoT applications. To implement an SNN model in NA-IDE, commonly used input data must be transformed for use in the SNN model. In this paper, we implemented a neural coding method encoder component that converts image data into a spike train signal and uses it as an SNN input. The decoder component is implemented to convert the output back to image data when the SNN model generates a spike train signal. If the decoder component uses the same parameters as the encoding process, it can generate static data similar to the original data. It can be used in fields such as image-to-image and speech-to-speech to transform and regenerate input data using the proposed encoder and decoder.