• Journal of Korean Association for Spatial Structures
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• v.10 no.4
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• pp.93-102
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• 2010

In this study, a smart sky-bridge composed of MR damper and FPS has been proposed and vibration control performance of a smart sky-bridge for the connected buildings was investigated. To this end, 10-story and 20-story building structures connected by a smart sky-bridge were selected as example structures and El Centro and Kobe earthquakes, which have near and far fault ground motion characteristics respectively, were used for time history analyses. In order to effectively control the smart sky-bridge, fuzzy logic controller was developed and multi-objective genetic algorithm was used to optimize fuzzy logic controllers. Based on optimization results, it has been seen that there is a trade-off between seismic responses of 10-story and 20-story buildings and a suite of Pareto optimal solutions of fuzzy logic controllers for seismic response control can be obtained by multi-objective genetic algorithm. It is shown from numerical study that seismic responses of adjacent buildings can be efficiently controlled by using a smart sky-bridge.

• The Journal of Korean Association of Computer Education
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• v.20 no.4
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• pp.77-84
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• 2017

This paper proposes a tool that can be used as a logical expression simplification tool that can be used for deepening learning of logic circuits and further utilized as a design automation tool for optimizing semiconductor parts. The simplification method of logical expressions proposed in this paper is to find common subexpressions existing in various logical expressions and reduce the repetitive use. Finally, the goal is to minimize the number of literals used in all logical expressions. These previous studies failed to produce a common subexpression embedded in the logical expressions because they only use division principle. The proposed method uses cubes with a Hamming distance of 3 to find the common subexpression embedded between logical expressions. Experiments using benchmark circuits show that the proposed method reduces the number of literals by as much as 47% when comparing simplifications with other methods.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.661-663
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• 2002

현대의 Deep-Submicron Technology(DSM)에선 배선에 관련된 문제, 예를 들어 crosstalk이나 노이즈 등이 큰 문제가 된다. 그리하여, 배선은 논리 구성요소들보다 더욱 중요한 위치를 차지하게 되었다. 우리는 이러한 배선을 고려하여 연산식을 최적화하기 위해 carry-save-adder(CSA)를 이용한 모듈 함성 알고리즘을 제시한다. 즉, 상위 단계에서 생성 된 규칙적인 배선 토폴로지를 유지하며 CSA간의 배선을 좀더 향상시키는 최적의 알고리즘을 제안한다. 우리는 우리의 이러한 방법으로 생성된 지연시간이 [1]에 가깝거나 거의 근접하는 것을 많은 testcase에서 보이며(배선을 포함하지 않은 상태에서), 그리고 그와 동시에 최종 배선의 길이가 짧고 규칙적인 구조를 갖는것을 보인다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.525-529
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• 1999

본 논문에서는 고속 FPGA 설계를 위한 논리 수준의 조합회로 합성 알고리듬을 제안한다. 제안 된 알고리듬은 회로의 지연시간을 줄이기 위해 critical path를 분할한 후 분할된 회로를 동시에 수행하는 구조의 회로를 생성한다. MCNC 표준 테스트 회로에 대한 실험에서 제안된 지연시간 최적화 알고리듬이 기존 알고리듬에 비해 지연시간이 평균 33.3 % 감소된 회로를 생성함을 보였다.

• Proceedings of the KIEE Conference
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• 2008.04a
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• pp.95-96
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• 2008

본 논문에서는 시계열 예측 공정의 모델링을 위해 Type-2 퍼지 논리 집합을 이용하여 불확실성 문제를 다룬다. 기존의 Type-1 퍼지 논리 시스템(Fuzzy Logic System, FLS)은 외부의 노이즈와 같은 불확실성에 민감한 단점이 있다. 그러나 Type 퍼지 논기 시스템은 불확실한 정보까지 멤버쉽 함수로 표현함으로서 효과적으로 취급할 수 있다. 여기서 불확실한 정보를 표현하기 위해 규칙의 전 후반부 멤버쉽 함수로 삼각형 형태의 Type-2 퍼지 집합을 사용한다. 전반부의 경우 HCM 클러스터링을 사용하여 입력 데이터들 간의 거리를 중심으로 멤버쉽 함수를 정의하고, 후반부는 입자 군집 최적화(Particle Swarm Optimization) 알고리즘으로 멤버쉽 함수의 정점을 동조한다. 제안된 모델은 표준 모델 평가에 주로 사용되는 가스로 시계열 데이터를 적용하고, 특정 데이터로 노이즈에 영향 받은 데이터를 사용하여 수치 석인 예를 보인다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.922-931
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• 2012

This paper studies a series of logical topology reconfiguration processes corresponding to a series of traffic demand changes in a ship backbone network. The proposed reconfiguration technique is to minimize costly changes of traffic forwarding paths and minimize the average hop distance of traffic forwarding paths in terms of ship backbone network performance simultaneously. Performance evaluation is conducted to illustrate the efficiency of the proposed reconfiguration technique. It shows that the proposed reconfiguration technique yields efficient performance in the entire series of reconfiguration processes.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10b
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• pp.562-565
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• 2006

가상기계(Virtual Machine)는 소프트웨어로 제작되어 논리적인 시스템 구성을 갖는 컴퓨터이기 때문에 그 수행 속도와 필요 저장 공간 측면에서 성능이 떨어질 수 밖에 없다. 따라서 가상기계의 성능에 있어서 보다 효율적인 코드로의 최적화가 중요하다. 본 논문에서는 가상기계 코드(Virtual Machine Code) 최적화를 위해 코드를 실행하여 얻을 수 있는 동적 정보인 프로파일링 데이터(Profiling Data)를 정의하고, 프로파일링 시스템을 설계하여 프로파일링 데이터를 가상기계 코드 최적화에 적용 할 수 있는 기반을 마련하였다. 나아가 EVM(Embedded Virtual Machine)에서 실행되는 SIL(Standard Intermediate Language) 코드를 대상으로 프로파일링 시스템을 구현하여 실제 가상 기계 코드에 대하여 프로파일링 데이터를 추출하였다.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1635-1645
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• 1999

In this paper, an intelligent resynthesis technique for timing optimization at the architecture-level has been studied. The proposed technique can remedy the problem which may occur in combinational timing optimization techniques applied to circuits which have the hierarchical subblock structure at the architectural-level. The approach first tries to maintain the original hierarchical subblock while minimizing the longest delay of whole circuit. This paper tries to find a new approach to timing optimization for circuits which have hierarchical structure at architectural-level, and has verified its effectiveness experimentally. We claim its usefulness from the fact that most designers design the circuits hierarchically due to the increase of design complexity.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.41-45
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• 2017

This paper presents a method of constructing the efficiency multiple output switching function of the combinational logic systems. The proposed method reduce the optimized input variable pair and output variable pair after we obtained the final multiple output switching function which was time based multiplexing and obtained the common multiple end node extension logic decision diagram. Also the proposed method have an advantage of the cost, input-output node number, circuit simplification, increment of the arithmetic speed, and more regularity and extensibility compare with previous method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.11
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• pp.4597-4603
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• 2010

A factorization is a very important part of multi-level logic synthesis. The number of literals in a factored form is an estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube nonkernel Boolean pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over previous other factorization methods.