• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.301-310
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• 2017

Quantum-dot cellular automata(QCA) is an alternative technology for implementing various computation, high performance, and low power consumption digital circuits at nano scale. In this paper, we propose a new universal gate in QCA. By using the universal gate, we propose a novel XOR gate which is reduced time/hardware complexity. The universal gate can be used to construct all other basic logic gates. Meanwhile, the proposed universal gate is designed by basic cells and a rotated cell. The rotated cell of the proposed universal gate is located at the central of 3-input majority gate structure. In this paper, we propose an XOR gate using three universal gates, although more than five 3-input majority gates are used to design an XOR gate using the 3-input majority gate. The proposed XOR gate is superior to the conventional XOR gate in terms of the total area and the consumed clock because the number of gates are reduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.

• Journal of IKEEE
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• v.18 no.3
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• pp.328-334
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• 2014

This paper proposes an optical encryption and decryption system for OFB(Output Feedback Block) encryption algorithm. The proposed scheme uses a dual-encoding technique in order to implement optical XOR logic operation. Also, the proposed method provides more enhanced security strength than the conventional electronic OFB method due to the huge security key with 2-dimensional array. Finally, computer simulation results of encryption and decryption are shown to verify the proposed method, and hence the proposed method makes it possible to implement more effective and stronger optical block encryption system with high-speed performance and the benefits of parallelism.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.6
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• pp.73-81
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• 2001

This study uses the distributed parameter systems resented by the spatial discretization technique. In this paper, the distributed parameter systems are converted into lumped parameter systems, End fast Walsh transform and the Picard's iteration method are allied to analysis the state of the systems. This thesis presents a new algorithm which usefully exercises the optimal contro1 in the distributed parameter systems. In exercising the optimal control of the distributed parameter systems, the excellent consequences are found without using the existing decentralized contro1 or hierarchical control method. This study can be applied to the linear time-varying systems and the non-linear systems. Farther researches are required to solve the problems of convergence in case of the numerous applicable intervals. The simulation proves the effectiveness of the proposed algorithm.

• Journal of Korea Spatial Information System Society
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• v.11 no.1
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• pp.79-86
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• 2009

The tuple of constraint database consists of constraint logical formula and it could process the presentation and query of the constraint database simply. Query operation processing shall include the constraint formula between related tuple such as selection, union, intersection of spatial data through the constraint database. However, this could produce the increasing of duplicated or unnecessary data. Hence, it will drive up the cost as per quality. This paper identified problems regarding query processing result in the constraint database. Also this paper suggested the tuple minimization summary method for result relation and analyzed the effects for efficient query processing. We were able to identify that the effectiveness of the query processing was enhanced by eliminating unnecessary constraint formula of constraint relation using the tuple minimization method.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.7
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• pp.1351-1362
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• 1992

Qualitative models in model-based expert system needs modeling paradigm which provides intelligent control of modeling assumptions and extracts robust inferences without quantitative information about the system to be modeled. Qualitative reasoning methodologies has proved the property of the completeness but not the soundness to the corresponding quantitative model. We propose new methodology of qualitative reasoning by introducing the concept of Centroid-Oriented Composite Interval to improve the soundness problem. Arithmetic operations and equivalence classes were composed using this definition. Qualitative simulation results were compared to Kuipers's results and the improvements in the soundness problem is verified.

• Journal of Korea Multimedia Society
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• v.9 no.8
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• pp.982-999
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• 2006

In this paper, we propose an automatic facial phrenology analysis and avatar drawing system based on internet using multi color information and face geometry. In the proposed system, we detect face using logical product of Cr and I which is a components of YCbCr and YIQ color model, respectively. And then, we extract facial feature using face geometry and analyze user's facial phrenology with the classification of each facial feature. And also, the proposed system can make avatar drawing automatically using extracted and classified facial features. Experimental result shows that proposed algorithm can analyze facial phrenology as well as detect and recognize user's face at real-time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1435-1442
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• 2006

The ideal method of safety evaluation is to verify results of execution against all possible operations within operating system, but it is impossible. However, the formal method can theoretically prove the safety on actual logic of operating system. Therefore we explain the contents of the art of the safety verification of security kernel, and make a comparative study of various standardized formal verification tools. And then we assigned PVS(Prototype Verification system) of SRI(Stanford Research Institute) to verify the safety of a modified BLP(Bell & LaPadula) model, the core access control model of multi-lavel based security kernel. Finally, we describe formal specification of the revised BLP model using the PVS, and evaluate the safety of the model by inspecting the specification of the PVS.