• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.5
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• pp.269-274
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• 2016

This paper proposes the development of a low frequency electronic hammer drive system that is used to prevent scaling or clogging in the hopper process. The electro-mechanical hammering driving method involves the generation of vibration and impact energy. The operation principles of the electromagnetic hammer were considered by parallel/series spring coefficient analysis and the amount of kinetic energy generated was calculated from the product of the equivalent spring constant, which is coupled with the E core and the gap of between the E core and I core. In addition, the Pulsation Driving algorithm was applied to the proposed electromagnetic hammer to obtain the maximizing kinetic energy. This algorithm was then implemented by a logical AND operation process and micro-controller (atmega128) built in functions with a timer interrupt and PWM generation function. The driving circuit of the electromagnetic hammer was designed using the H-bridge type IGBT circuit. The experimental test was performed by usefulness of the developed electromagnetic hammer systems with the acceleration measurement method. The experimental result showed that the proposed system has good kinetic energy generation performance and can be applied to the hopper process.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.1-6
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• 2021

The paper proposes the design of AES-based encryption chip for IoT security. ROM based S-Box implementation occurs a number of memory space and some delay problems for its access. In this approach, S-Box is designed by pipeline structure on composite field GF((22)2) to get faster calculation results. In addition, in order to achieve both higher throughput and less delay, shared S-Box are used in each round transformation and the key scheduling process. The proposed AES crypto-processor is described in Veilog-HDL, and Xilinx ISE 14.7 tool is used for logic synthesis by using Xilinx XC6VLX75T FPGA. In order to perform the verification of the crypto-processor, the timing simulator(ModelSim 10.3) is also used.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.103-113
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• 2007

In this paper, we present a security analysis of Lightweight RFID Mutual Authentication Protocols-LMAP[10], $M^2AP$[11], EMAP[12]. Based on simple logic operations, the protocols were designed to be suitable for lightweight environments such as RFID systems. In [8,9], it is shown that these protocols are vulnerable to do-synchronization attacks with a high probability. The authors also presented an active attack that partially reveals a tag's secret values including its ID. In this paper, we point out an error from [9] and show that their do-synchronization attack would always succeed. We also improve the active attack in [9] to show an adversary can compute a tag's ID as well as certain secret keys in a deterministic way. As for $M^2AP$ and EMAP, we show that eavesdropping $2{\sim}3$ consecutive sessions is sufficient to reveal a tag's essential secret values including its ID that allows for tracing, do-synchronization and/or subsequent impersonations.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.291-300
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• 2017

Quantum-dot cellular automata(QCA) is a computing model designed to be similar to cellular automata, and an alternative technology for next generation using high performance and low power consumption. QCA is undergoing various studies with recent experimental results, and it is one of the paradigms of transistors that can solve device density and interconnection problems as nano-unit materials. An XOR gate is a gate that operates so that the result is true when either one of the logic is true. The proposed XOR gate consists of five layers. The first layer consists of OR gates, the third and fifth layers consist of AND gates, and the second and fourth layers are designed as passages in the middle. The half adder consists of an XOR gate and an AND gate. The proposed half adder is designed by adding two cells to the proposed XOR gate. The proposed half adder consists of fewer cells, total area, and clock than the conventional half adder.

• Education of Primary School Mathematics
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• v.27 no.1
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• pp.57-74
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• 2024

This paper analyzed the programming education specialized lessons presented in two types of elementary school mathematics textbooks according to the revised Japanese curriculum in 2017. First, this paper presented in detail how each activity is connected to Korean mathematics areas, what elements of mathematics can be learned through programming education, how each activity is structured, and how the actual programming according to the textbook activities is structured. In Japanese textbooks, geometry and measurement areas were presented the most among Korean mathematics content areas, and mathematical elements such as sequences, rules, and algorithms were most implemented for learning. Digital learning tools that make up actual programming present more elements than those presented in the textbooks and are presented in great detail so that students can do actual programming. Lastly, in blocks, motion, control, and calculation blocks were used a lot. Based on these research results, this study provides implications when conducting programming-related education in Korea.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• KIPS Transactions on Software and Data Engineering
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• v.6 no.2
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• pp.103-116
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• 2017

In this paper, we present the design and implementation of a large-scale qualitative spatial reasoner, which can derive new qualitative spatial knowledge representing both topological and directional relationships between two arbitrary spatial objects in efficient way using Aparch Spark SQL. Apache Spark SQL is well known as a distributed parallel programming environment which provides both efficient join operations and query processing functions over a variety of data in Hadoop cluster computer systems. In our spatial reasoner, the overall reasoning process is divided into 6 jobs such as knowledge encoding, inverse reasoning, equal reasoning, transitive reasoning, relation refining, knowledge decoding, and then the execution order over the reasoning jobs is determined in consideration of both logical causal relationships and computational efficiency. The knowledge encoding job reduces the size of knowledge base to reason over by transforming the input knowledge of XML/RDF form into one of more precise form. Repeat of the transitive reasoning job and the relation refining job usually consumes most of computational time and storage for the overall reasoning process. In order to improve the jobs, our reasoner finds out the minimal disjunctive relations for qualitative spatial reasoning, and then, based upon them, it not only reduces the composition table to be used for the transitive reasoning job, but also optimizes the relation refining job. Through experiments using a large-scale benchmarking spatial knowledge base, the proposed reasoner showed high performance and scalability.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.127-132
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• 2011

In this paper, we propose a novel method of adult image classification by combining skin color regions and edges in an input image. The proposed method consists of four steps. In the first step, initial skin color regions are detected by logical AND operation of all skin color regions detected by the existing methods of skin color detection. In the second step, a skin color probability map is created by modeling the distribution of skin color in the initial regions. Then, a binary image is generated by using threshold value from the skin color probability map. In the third step, after using the binary image and edge information, we detect final skin color regions using a region growing method. In the final step, adult image classification is performed by support vector machine(SVM). To this end, a feature vector is extracted by combining the final skin color regions and neighboring edges of them. As experimental results, the proposed method improves performance of the adult image classification by 9.6%, compared to the existing method.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.274-292
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• 2011

This paper proposes an efficient coding method of the depth-map which is different from the natural images. The depth-map are so smooth in both inner parts of the objects and background, but it has sharp edges on the object-boundaries like a cliff. In addition, when a depth-map block is decomposed into bit planes, the characteristic of perfect matching or inverted matching between bit planes often occurs on the object-boundaries. Therefore, the proposed depth-map coding scheme is designed to have the bit-plane unit coding method using the adaptive XOR method for efficiently coding the depth-map images on the object-boundary areas, as well as the conventional DCT-based coding scheme (for example, H.264/AVC) for efficiently coding the inside area images of the objects or the background depth-map images. The experimental results show that the proposed algorithm improves the average bit-rate savings as 11.8 % ~ 20.8% and the average PSNR (Peak Signal-to-Noise Ratio) gains as 0.9 dB ~ 1.5 dB in comparison with the H.264/AVC coding scheme. And the proposed algorithm improves the average bit-rate savings as 7.7 % ~ 12.2 % and the average PSNR gains as 0.5 dB ~ 0.8 dB in comparison with the adaptive block-based depth-map coding scheme. It can be confirmed that the proposed method improves the subjective quality of synthesized image using the decoded depth-map in comparison with the H.264/AVC coding scheme. And the subjective quality of the proposed method was similar to the subjective quality of the adaptive block-based depth-map coding scheme.