• Journal of Advanced Navigation Technology
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• v.22 no.2
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• pp.154-162
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• 2018

The multiplier circuit is necessary to estimate degradation status of electronic cards in nuclear power plant, but its accuracy is not easy in processing those functions to multiply two input signals. What is important in multiplier circuit is that the multiplication result must be accurate and its linearity must be perfect. We developed and proposed excellent linearity multiplier circuit using operational amplifiers and transistor characteristics, and then proved its validity in this paper. We have made efforts to eliminate nonlinearity components of semiconductors with this circuit in order to ensure excellent linearity of developed multiplier circuit. We conducted multiplication operations through simulation, applying adequate values to each component in order to verify the circuit composed of that method. We showed step-by-step output signals, and then compared the logical analyses and measuring results as simulation results. We confirmed that this method is superior to existing multiplication or linearity.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.3
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• pp.41-48
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• 2004

Finite field multiplication and division are important arithmetic operation in error-correcting codes and cryptosystems. The elements of the finite field GF($2^m$) are represented by bases with a primitive polynomial of degree m over GF(2). We can be easily realized for multiplication or computing multiplicative inverse in GF($2^m$) based on a normal basis representation. The number of product terms of logic function determines a complexity of the Messay-Omura multiplier. A normal basis exists for every finite field. It is not easy to find the optimal normal element for a given primitive polynomial. In this paper, the generating method of normal basis is investigated. The normal bases whose product terms are less than other bases for multiplication in GF($2^m$) are found. For each primitive polynomial, a list of normal elements and number of product terms are presented.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.409-416
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• 2024

With the expansion of floating-point operation requirements for fast high-speed data signal processing and logic operations, the speed of the floating-point operation unit is the key to affect system operation. This paper studies the performance characteristics of different floating-point multiplier schemes, completes partial product compression in the form of carry and sum, and then uses a carry look-ahead adder to obtain the result. Intel Quartus II CAD tool is used for describing Verilog HDL and evaluating performance results of the floating point multipliers. Floating point multipliers are analyzed and compared based on area, speed, and power consumption. The FMAX of modified Booth encoding with Wallace tree is 33.96 Mhz, which is 2.04 times faster than the booth encoding, 1.62 times faster than the modified booth encoding, 1.04 times faster than the booth encoding with wallace tree. Furthermore, compared to modified booth encoding, the area of modified booth encoding with wallace tree is reduced by 24.88%, and power consumption of that is reduced by 2.5%.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.170-172
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• 2012

실시간 시스템(real-time system)은 논리적 연산을 일정한 시간적 제약 하에서 수행하는 시스템이다. 시간적 제약을 충족하도록 주기적 태스크(periodic task)를 스케줄(schedule)할 때 일반적으로 태스크 오프셋(initial offset)이 0 이거나 고정된 것으로 가정한다. 그러나 오프셋에 약간의 유연성을 허용함으로써 태스크들의 평균 응답 시간을 줄일 수도 있다. 이 논문에서는 주기적 태스크의 오프셋을 주어진 허용 범위 안에서 선택하여 평균 응답 시간(response time)을 최적화할 수 있음을 보이고, 임의의 태스크 집합에 대하여 최적 오프셋이 존재하는 좁은 범위를 제시한다.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2009.04a
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• pp.396-399
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• 2009

본 논문의 연구 목적은 생물의 진화 현상을 모방한 진화전략 알고리즘을 이용하여 돔형 트러스 구조물을 최적화 설계하는 것이다. 최적화 방법으로 부재 단면적의 최적화 값을 찾음으로써 최적 목적값 또는 최소 구조물 중량을 산출하는데 목적이 있다. 진화전략 알고리즘은 1960년대 중반, 실수기반 매개변수의 최적화로부터 소개되어 1970년대 많은 발전을 하였다. 진화전략은 컴퓨터 시스템 최적화 알고리즘 연구분야에서 많이 활용되며, 더불어 사용되는 유전자 알고리즘과는 다른 몇 개의 연산자를 가지고 있다. 본 논문에서는 진화전략에서 사용되는 연산자를 소개하고 연산자간의 논리 흐름과 수치예제로써 최적설계의 적합성을 확인해볼 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.787-794
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• 1999

This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.685-691
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• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• The Transactions of the Korea Information Processing Society
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• v.2 no.2
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• pp.247-253
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• 1995

An efficient algorithm for clipping 2D lines on a rectangular window is proposed. It is suitable for displaying images consisted of many lines for it can reduce the number of arithmetic and logical operations. The algorithm is compared with the Cohen-Sutherland algorithm and it was proved to be efficient.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.5
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• pp.43-49
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• 1983

In this paper, an architecture for high-speed RNS multiplier were proposed by using com-binational logic circuit. The optimum conditions of moduli set which could be saved hardware and operation time were also considered. In the case of RRNS multiplier, output translation could be achieved effectively by means of the modified CRT with magnitude index. It is shown that the estimated multiplication time is about 31.7 ns in NRNS, whereas 47.95 ns in RRNS, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.322-324
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• 2006

유비쿼터스 컴퓨팅은 사물에 컴퓨터 기능이 내장되어 언제, 어디에서나, 어느 장치로도 편리하게 주변 환경으로부터 서비스를 사용할 수 있게 하는 정보기술의 패러다임이다. 이를 위해선 상황인지가 전제되어야 하는데 여기서 상황인지라 함은 시스템의 다양한 센서 정보를 바탕으로 스스로 상황(Context)을 인지하는 것으로서, 그 정의에 있어서, 아직 논란이 많으나 지능형 서비스를 위한 중요한 개념이다. 본 논문에서는 센서로부터 바로 생성된 Raw Context 정보를 Low-Level Context라고 하고 이를 복합(Fusion)하여 이미 알려진 High-Level Context로 분류하는 논리적 연산을 추론에 기반한 상황인지로서 정의한다. 이때 센서 정보를 통해 특정한 상황정보를 추론하기 위한 모델을 설계하여 상황인지 미들웨어에 적용시켜 보고 그에 따른 효율적인 구조를 기술한다.