• Electrical & Electronic Materials
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• v.6 no.1
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• pp.28-33
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• 1993

Short channel 비휘발성 SNOSFET EEPROM 기억소자를 CMOS 1 Mbit 설계규칙에 따라 제작하고 특성과 응용을 조사하였다. 논리 어레이를 실현하기 위한 SNOSFET는 4단자와 2단자 비휘발성 메모리 셀로 구성하고 이에 대한 기록과 소거 특성을 조사하였다. 결과적으로 4단자 소자와 2단자 소자의 메모리 윈도우는 각각 기록과 소거에 의하여 "1"상태와 "0"상태로 동작되는 저전도 상태와 거전도 상태를 나타냈다. 4단자 2 x 2 메트릭스 어레이는 양극성으로 동작하였으며 2단자 2 x 2 메트릭스 어레이는 단극성으로 동작하였다.릭스 어레이는 단극성으로 동작하였다.

• Electrical & Electronic Materials
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• v.4 no.3
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• pp.259-266
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• 1991

1.5.mu.m의 찬넬길이를 갖는 short channel 비휘발성 SNOSFET 기억소자를 기존의 CMOS 1 Mbit 공정기술을 이용하여 제작하고 I$_{d}$-V$_{d}$ 및 I$_{d}$- V$_{g}$특성과 스윗칭 및 기억유지특성을 조사하였다. 그 결과 제작한 소자는 논리회로 설계에 적절한 전도특성을 가졌으며 스윗칭시간은 인가전압의 크기에 의존함을 보였다. 그리고 3V의 memory window 크기를 얻기 위해서 V$_{w}$ =+34V, t$_{w}$ =50.mu.sec 및 V$_{e}$=-34V, t$_{e}$=500.mu.sec의 펄스전압으로 각각 write-in과 erase할 수 있었다. 또한 기억상태는 10년이상 유지할 수 있음을 알 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.108-116
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• 1989

The simulator described here-LOSIM(LOgic SIMulator)-was developed to verify the logic design for VLSI(Very Large Scale Integrated) circuits at mixed level. In this paper, we present a modeling approach to obtain more accurate results than conventional logic simulators [5-6,9] for general elements, functional elements, transmission gates and tri-state gates using eight signal values and two gignal strengths. LOSIM has the capability which can perform timing and hazard analysis by using assignable rise and fall delays. We also prosent an efficient algorithm to accurately detectdynamic and static hazards which may be caused by the circuit delays. Our approach is based on five logic values and the scheduled time. LOSIM has been implemented on a UN-3/160 workstation running Berkeley 4.2 UNIX, and the program is written in C language. Static RAM cell and asynchronous circuit are illustrated as an example.

• Prospectives of Industrial Chemistry
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• v.23 no.6
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• pp.25-36
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• 2020

용액공정을 통해 유기 전자소자를 대면적으로 제조하는 것은 다양한 장치 구성 요소(반도체, 절연체, 도체)의 패터닝 및 적층이 필요하기 때문에 매우 어려운 과제이다. 본 연구에서는 4개의 광 가교 기능기를 가지는 3차원 사면체 가교제인 (2,2-bis(((4-azido-2,3,5,6-tetrafluorobenzoyl)oxy)methyl)propane-1,3-diyl bis(4-azido-2,3,5,6-tetrafluorobenzoate) (4Bx)를 활용하여 용액공정을 기반으로 형성된 전자재료 박막을 고해상도로 패터닝 및 적층하는 기술을 개발하고, 이를 사용하여 고분자 박막 트랜지스터(PTFTs) 및 논리회로 어레이 제작을 진행하였다. 4Bx는 다양한 용액공정이 가능한 전자재료와 용매에 쉽게 혼합될 수 있으며, 자외선(UV)에 의해 가교제가 광 활성화되어 전자재료와 가교 결합을 형성할 수 있다. 4Bx는 기존의 2개의 광 가교 기능기를 갖는 가교제에 비해 높은 가교 효율로 인해 적은 양을 첨가하여도 완전하게 가교된 전자재료 박막을 형성할 수 있어 전자재료의 고유한 특성을 보존할 수 있다. 더욱이, 가교된 전자재료 박막은 화학적 내구성이 향상되어 고해상도 미세 패터닝을 할 수 있을 뿐만 아니라 용액공정을 통해 전자소자를 구성하는 전자재료의 적층이 가능하다. 4Bx의 광 가교 방법은 전용액공정을 통한 전자소자의 제작에 대한 혁신적인 방안을 제시한다.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.47-53
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• 2004

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.6
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• pp.589-594
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• 1992

This paper offers the simplification method of Multiple-Valued logic function based on M-AND,M-OR, NOT operation presented by Lukasiewicz. First in performing the simplification the result is different by the method to arrange Cube, the method to find the most effective adjacent term if, most of all, important in simplification. According to this method, the two-variable multiple-valued logic function given by truth table is decomposed. The simplification method in this paper proves that the number of devices and cost is considerably reduced comparing with the existing method 141 to realize the same logic functions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.298-310
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• 1997

Most of the available delay fault simulators for scan environments rely on the use of enhanced scan flip-flops and exclusively consider circuits composed of only discrete gates. In this research, a new path delay fault simulation algorithm using new logic values is devised to enlarge the scope to the VLSI circuits which consist of CMOS elements. Based on the proposed algorithm, a high speed path delay fault simulator for standard scan environments is developed. The experimental results show the new simulator is efficient and accurate.