• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.40-46
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• 2006

Latching optical switches and optical logic gates AND and OR are demonstrated, for the first time, by the monolithic integration of a vertical cavity lasers with depleted optical thyristor structure, which have not only a low threshold current with 0.65mA, but also a high on/off contrast ratio more than 50dB. By simple operating technique with changing a reference switching voltage, this single device operates as two logic functions, optical logic AND and OR. The thyristor laser fabricated using the oxidation process achieved a high optical output power efficiency and a high sensitivity to the optical input light.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.138-138
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• 2017

차세대 CMOS 소자의 지속적인 고직접화를 위해서는 높은 gate capacitance와 낮은 gate leakage current를 확보를 위한, 적절한 metal gate electrode와 high-k dielectric 물질의 개발이 필수적으로 요구된다. 특히, gate dielectric으로 적용하기 위한 다양한 high-k dielectric 물질 후보군 중에서, 높은 dielectric constant와, 낮은 leakage current, 그리고 Si과의 우수한 열적 안정성을 가지는 Zr silicates 또는 Hf silicates(ZrSiO4와 HfSiO4) 물질이 높은 관심을 받고 있으며, 이를 원자층 증착법을 통해 구현하기 위한 노력들이 있어왔다. 그러나, 현재까지 보고된 원자층 증착법을 이용한 Zr silicates 및 Hf silicates 공정의 경우, 개별적인 Zr(또는 Hf)과 Si precursor를 이용하여 ZrO2(또는 HfO2)과 SiO2를 반복적으로 증착하는 방식으로 Zr silicates 또는 Hf silicates를 형성하고 있어, 전체 공정이 매우 복잡해지는 문제점 뿐 아니라, gate dielectric 내에서 Zr과 Si의 국부적인 조성 불균일성을 야기하여, 제작된 소자의 신뢰성을 떨어뜨리는 문제점을 나타내왔다. 따라서, 본 연구에서는 이러한 문제점을 개선하기 위하여, 하나의 precursor에 Zr (또는 Hf)과 Si 원소를 동시에 가지고 있는 DNS-Zr과 DNS-Hf bimetallic precursor를 이용하여 새로운 ZrSiO4와 HfSiO4 ALD 공정을 개발하고, 그 특성을 살펴보고자 하였다. H2O와 O3을 reactant로 사용한 원자층 증착법 공정을 통하여, Zr:Si 또는 Hf:Si의 화학양론적 비율이 항상 일정한 ZrSiO4와 HfSiO4 박막을 형성할 수 있었으며, 이들의 전기적 특성 평가를 진행하였으며, dielectric constant 및 leakage current 측면에서 우수한 특성을 나타냄을 확인할 수 있었다. 이러한 결과를 바탕으로, bimetallic 전구체를 이용한 ALD 공정은 차세대 고성능 논리회로의 게이트 유전물질에 응용이 가능할 것으로 판단된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.1-11
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• 2002

A multi-section DFB-LD shows optical bistability subject to externally injected light signal, then it has potential applications such as wavelength conversion and optical logic gates. In this paper, we have studied the optical bistability in multi-section DFB-LD using split-step time-domain model. It is confirmed that the multi-section DFB-LD, which is excited inhomogeneously, shows bistability. The optical bistable characteristics are investigated when input light is injected into a absorptive region. Simulation results show that multi-section DFB-LD works as a flip-flop depending on the set-reset optical pulse which has a few ns in switching time and a few pj in switching energy, so that it can act as a optical logic device. Besides, if we change the carrier lifetime and the differential gain coefficient, it is expected that the response time of optical output signal can be reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.1-9
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• 2012

Memristor which is known as fourth basic circuit element has been developed recently but its electrical characteristics are not still fully understood. Memristor has the incremental and decremental feature of the resistance depending upon the connected polarities. Also, its operational behavior become diverse depending on its connection topologies. In this work, electrical characteristics of diverse types of serial and parallel connections are investigated using the HP $TiO_2$ model. The characteristics are analyzed with pinched hystersis loops on the V-I plane when sine input signal is applied. The results of the work would be utilized usefully for analyzing the characteristics of memristor element and applications to logic circuit and neuron cells.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.24-30
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• 2007

Latching optical switches and optical logic gates with AND or OR, and the INVERT functionality are demonstrated, for the first time, by the monolithic integration of a differential typed vertical cavity laser with depleted optical thyristor (VCL-DOT) structure with a low threshold current of 0.65 mA, a high slope efficiency of 0.38 mW/mA, and high sensitivity to input optical light. Many kinds of logic functions (AND, OR, NAND, NOR, and INVERT) are experimentally demonstrated using a differential switching operation scheme changing the intensity of a reference input beam without any changes of electrical circuits.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.431-434
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• 2001

단층 퍼셉트론이 처음 개발되었을 때, 간단한 패턴을 인식하는 학습 기능을 가지고 있기 장점 때문에 학자들의 관심을 끌었다. 단층 퍼셉트론은 한 개의 소자를 이용해서 이진 논리를 가중치(weight)의 변경만으로 모두 표현할 수 있는 장점 때문에 영상처리, 패턴인식, 장면인식 등에 이용되어 왔다. 최근에, 역전파학습(Back-Propagation Learning)알고리즘이 이진 공간내의 매핑 문제에 적용되고 있다. 그러나, 역전파 학습알고리즘은 연속공간 내에서 긴 학습시간과 비효율적인 수행의 문제를 가지고 있다. 일반적으로 역전파 학습 알고리즘은 간단한 이진 공간에서 매핑하기 위해서 많은 반복과정을 요구한다. 역전파 학습 알고리즘에서는 은닉층의 뉴런의 수는 주어진 문제를 해결하기 위해서 우선순위(prior)를 알지 못하기 때문에 입력층과 출력층내의 뉴런의 수에 의존한다. 따라서, 3층 신경회로망의 적용에 있어 가장 중요한 문제중의 하나는 은닉층내의 필요한 뉴런수를 결정하는 것이고, 회로망 합성과 가중치 결정에 대한 적절한 방법을 찾지 못해 실제로 그 사용 영역이 한정되어 있었다. 본 논문에서는 패턴 분류를 위한 새로운 학습방법을 제시한다. 훈련입력의 기하학적인 분석에 기반을 둔 이진 신경회로망내의 은닉층내의 뉴런의 수를 자동적으로 결정할 수 있는 NETLA(Newly Expand and Truncate Learning Algorithm)라 불리우는 기하학적 학습알고리즘을 제시하고, 시뮬레이션을 통하여, 제안한 알고리즘의 우수성을 증명한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.36-42
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• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials with all non-zero coefficients over finite field GF($P^m$). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of $(m+1)^2$ identical cells, each cell consists of one mod(p) additional gate and one mod(p) multiplicative gate. Proposed multiplier need one mod(p) multiplicative gate delay time and m mod(p) additional gate delay time not clock. Also, our architecture is regular and possesses the property of modularity, therefore well-suited for VLSI implementation.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.21 no.12
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• pp.1608-1614
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• 1997

The fluidic flow meter detects the gas flow rate based on the principle of fluidic oscillation instead of the conventional displacement method. It has many merits: wide rangeability, no moving mechanical parts and calibration insensitive to physical properties of fluids. The width of nozzle, size of oscillation chamber, size of target, width of outlet are tested to obtain the effects of jet oscillation on the fluidic flow meter. As the width of nozzle is too wide compared with the size of target, jet oscillation is unstable. The oscillation frequency decreases as the distance between the nozzle and target increases and also as the distance between target and outlet contraction increases. Two different vortexes exist in the front and the rear regions of the target, and they affect the oscillation frequency. The outlet contraction is very important, because the feedback flow is generated by the blocking of the flow. As the width of outlet increases, the jet oscillation frequency decreases. The linearity of this tested flow meter is quite good.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.425-432
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• 1995

In this paper we propose a design and implementation technique of a universal automatic test pattern generator(UATPG) which is well suited for VLSI digital circuits. UATPG is designed to extend the capabilities of the existing APTG and to provide a convenient environment to computer-aided design(CAD) users. We employ heuristic techniques in line justification and fault propagation for functional gates during test pattern generation for a target fault. In addition, the flip-flops associated with design for testability (DFT) are exploited for pseudo PIs and pseudo POs to enhance the testabilities of VLSI circuits. As a result, UATPG shows a good enhancement in convenient usage and performance.