• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.4
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• pp.501-509
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• 2010

A floating crane is a crane-mounted ship and is used to assemble or to transport heavy blocks in shipyards. In this paper, the static and dynamic response of a floating crane and a heavy block that are connected using elastic booms and wire ropes are described. The static and dynamic equations of surge, pitch, and heave for the system are derived on the basis of flexible multibody system dynamics. The equations of motion are fully coupled and highly nonlinear since they involve nonlinear mass matrices, elastic stiffness matrices, quadratic velocity vectors, and generalized external forces. A floating frame of reference and nodal coordinates are employed to model the boom as a flexible body. The nonlinear hydrostatic force, linear hydrodynamic force, wire-rope force, and mooring force are considered as the external forces. For numerical analysis, the Hilber-Hughes-Taylor method for implicit integration is used. The dynamic responses of the cargo are analyzed with respect to the results obtained by static and numerical analyses.

• The Journal of the Convergence on Culture Technology
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• v.10 no.1
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• pp.471-476
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• 2024

With the spread of various smart devices and computing devices, big data generation is occurring widely. Machine learning is an algorithm that performs reasoning by learning data patterns. Among the various machine learning algorithms, the algorithm that attracts attention is deep learning based on neural networks. Deep learning is achieving rapid performance improvement with the release of various applications. Recently, among deep learning algorithms, attempts to analyze data using graph structures are increasing. In this study, we present a graph generation method for transferring to a deep learning network. This paper proposes a method of generalizing node properties and edge weights in the graph generation process and converting them into a structure for deep learning input by presenting a matricization We present a method of applying a linear transformation matrix that can preserve attribute and weight information in the graph generation process. Finally, we present a deep learning input structure of a general graph and present an approach for performance analysis.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.89-94
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• 2009

This paper proposes the algorithms that design the highly digital logic circuit and assign the code to each node of DCG(Directed Cyclic Graph) of length ${\zeta}$. The conventional algorithm have some problems, so this paper introduce the matrix equation from DCG of length ${\zeta}$ and proposes highly digital logic circuit design algorithms according to the DCG of length ${\zeta}$. Using the proposed circuit design algorithms in this paper, it become realized that was able to design from former algorithm. Also, making a comparison between the circuit using former algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed circuit design algorithm in this paper, it is possible to design current that DCG have natural number, so it have the following advantages, reduction of the circuit input/output digits, simplification of circuit composition, reduction of computation time and cost. And we show comparability and verification about this paper's algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.20-29
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• 1998

This paper proposes the algorithms that design the highly parallel multiple-valued logic curcuit and assign the code to each node of DCG(Directed Cyclic Graph) of length 1. The conventional Nakajima's algorithm have some problems, so this paper introduce the matrix equation from DCG of length 1 and proposes circuit design algorithms according to the DCG of length 1. Using the proposed circuit design algorithms in this paper, it become realized that was not able to design from Nakajima's algorithm. Also, making a comparision between the circuit design using Nakajima's algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed curcuit design algorithm in this paper, it is possible to design curcuit that DCG have natural number, so it have the following advantages; reduction of the curcuit input/output digits, simplification of curcuit composition, reduction of computation time and cost. And we show compatibility and verification about this paper's algorithm.

• Journal of the Korean Institute of Intelligent Systems
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• v.5 no.2
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• pp.44-57
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• 1995

In this paper GFI (Generalized Fuzzy Isodata) and FI (Fuzzy Isodata) algorithms are studied and applied to the tire tread pattern classification problem. GFI algorithm which repeatedly grouping the partitioned cluster depending on the fuzzy partition matrix is general form of GI algorithm. In the constructing the binary tree using GFI algorithm cluster validity, namely, whether partitioned cluster is feasible or not is checked and construction of the binary tree is obtained by FDH clustering algorithm. These algorithms show the good performance in selecting the prototypes of each patterns and classifying patterns. Directions of edge in the preprocessed image of tire tread pattern are selected as features of pattern. These features are thought to have useful information which well represents the characteristics of patterns.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1392-1398
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• 2008

This paper presents a Petri Net (PN) based disassembly sequence planning model with precedence operations. All feasible disassembly sequences are generated by a disassembly tree and a disassembly sequence is determined using the disassembly precedence and disassembly value matrix, The precedence of disassembly operations is determined through a disassembly tree and the value of disassembly is induced by economic analysis in the end-of-life phase. To solve the disassembly sequence planning model with precedence operations, a heuristic algorithm based on PNs is developed. The developed algorithm generates and searches a partial reachability graph to arrive at an optimal or near-optimal disassembly sequence based on the firing sequence of transitions of the PN model. A refrigerator is shown as an example to demonstrate the effectiveness of proposed model.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.88-93
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• 2016

This paper presents a method of constructing the highly performance switching circuit(HPSC) over finite fields. The proposed method is as following. First of all, we extract the input/output relationship of linear characteristics for the given digital switching functions, Next, we convert the input/output relationship to Directed Cyclic Graph using basic gates adder and coefficient multiplier that are defined by mathematical properties in finite fields. Also, we propose the new factorization method for matrix characteristics equation that represent the relationship of the input/output characteristics. The proposed method have properties of generalization and regularity. Also, the proposed method is possible to any prime number multiplication expression.

• Proceedings of the KOR-KST Conference
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• 1998.10a
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• pp.11-20
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• 1998

정적 통행배분모형은 도로 건설 등 공급부문에의 적용은 가능하나 통행량 및 혼잡의 시간적 공간적 변화를 고려하지 못하여 수요관리에서는 교통량 및 비용에 대한 관측치와 모형의 결과치가 상이한 문제가 있다. 이에 동적배분모형의 다양한 접근방법이 시도되고 있는데 그 중 Simulation기법을 개발하고자 하였다. 모형은 개별차량의 시공간상 움직임을 포현하고자 절대시간이 가장 이른 차량순으로 시뮬레이션을 함으로써 선입선출(FIFO)을 가능하게 하였다. 각 차량별 지체시간의 계산은 대기행렬 이론을 기초로 한 누적곡선법을 적용하여 도출하였다. 개별차량 Simulation은 시간축으로 확장된 연속류 Network상에서 각 차량의 도착 및 출발할 노드와 시간대를 결정하면 모든 지점에서 누적도착, 출발곡선을 그릴 수 있으며 이를 통해 도로구간에 있어 시간대별 통행시간, 밀도, 속도 등을 파악할 수 있다. 또한 합류부의 용량와 와해현상과 분류부의 용량변화현상 제약 및 Queue길이 제약이 이루어지도록 하였다. 개발된 모형의 검증은 영동대교 북단 강변도로 진출입부 자료를 실측하여 사용하였다. 모형은 합류부 용량와해의 적용 전과 후의 결과를 각각 실측치와 비교하였다. 용량와해현상을 적용한 모형에서 MAPE 10%미만의 우수한 예측력을 보였다. 이는 누적곡선을 이용한 Simulation모형이 현실에 가까움을 의미하는 것이며, 합류부 용량와해현상의 관계식을 보다 정교하게 도출하고 분류부에도 이를 적용한다면 모형의 예측력은 더욱 향상될 것으로 보인다.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2789-2791
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• 2001

데이터 마이닝을 통해 우리는 숨겨진 지식, 예상되지 않았던 경향 그리고 새로운 법칙들을 방대한 데이터에서 이끌어내고자 한다. 본 논문에서 우리는 사용자의 구매 패턴을 발견하여 사용자가 원하는 상품을 미리 예측하여 추천하는 알고리즘을 소개하고자 한다. 제안하고 있는 item dependency map은 구매된 상품간의 관계를 수식화 하여 행렬의 형태로 표현한 것이다. Item dependency map의 값은 사용자가 A라는 상품을 구매한 후 B상품을 살 확률이다. 이런 정보를 가지고 있는 item dependency map은 홉필드 네트윅(Hopfield network)에서 연상을 위한 패턴 값으로 적용된다. 홉필드 네트웍은 각 노드사이의 연결가중치에 기억하고자 하는 것들을 연상시킨 뒤 어떤 입력을 통해서 전체 네트워크가 어떤 평형상태에 도달하는 방식으로 작동되는 신경망 중의 하나이다. 홉필드 네트웍의 특징 중의 하나는 부분 정보로부터 전체 정보를 추출할 수 있는 것이다. 이러한 특징을 가지고 사용자들의 일반적인 구매패턴을 일부 정보만 가지고 예측할 수 있다. Item dependency map은 홉필드 네트윅에서 사용자들의 그룹별 패턴을 학습하는데 사용된다. 따라서 item dependency map이 얼마나 사용자 구매패턴에 대한 정보를 가지고 있는지에 따라 그 결과가 결정되는 것이다. 본 논문은 정확한 item dependency map을 계산해 내는 알고리즘을 주로 논의하겠다.