• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.1003-1012
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• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• Korean Chemical Engineering Research
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• v.60 no.2
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• pp.300-307
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• 2022

Time-resolved serial femtosecond crystallography (TR-SFX) is a powerful technique for determining temporal variations in the structural properties of biomacromolecules on ultra-short time scales without causing structure damage by employing femtosecond X-ray laser pulses generated by an X-ray free electron laser (XFEL). The mixing rate of reactants and biomolecule samples, as well as the hit rate between crystal samples and x-ray pulses, are critical factors determining TR-SFX performance, such as accurate image acquisition and efficient sample consumption. We here develop two distinct sample delivery systems that enable ultra-fast mixing and on-demand droplet injecting via pneumatic application with a square pulse signal. The first strategy relies on inertial mixing, which is caused by the high-speed collision and subsequent coalescence of droplets ejected through a double nozzle, while the second relies on on-demand pneumatic jetting embedded with a 3D-printed micromixer. First, the colliding behaviors of the droplets ejected through the double nozzle, as well as the inertial mixing within the coalesced droplets, are investigated experimentally and numerically. The mixing performance of the pneumatic jetting system with an integrated micromixer is then evaluated by using similar approaches. The sample delivery system devised in this work is very valuable for three-dimensional biomolecular structure analysis, which is critical for elucidating the mechanisms by which certain proteins cause disease, as well as searching for antibody drugs and new drug candidates.

• The Journal of the Korea Contents Association
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• v.14 no.10
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• pp.438-453
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• 2014

This paper proposes a system to translate an RDB into an OWL ontology which enables the users to navigate the ontology in GUI. In order to accomplish the goals mentioned previously, the system overcame two difficulties. First, our system defines a new mapping algorithm to map between DB elements and ontology ones. Comparing with existing solutions, our algorithm is able to generate ontologies from more DB structures. Second, our system provides the same data generated by a reasoner to the users. Note that this operation does not load ABox ontology on a reasoner. In addition, Tableau-based reasoners have the tractability problem on a large ABox (e.g., large ABoxes translated from DBs practically cannot be served). To solve this, our system internally runs SQL queries to retrieve the same data as the one from a reasoner every time ABox elements are queried.

• The KIPS Transactions:PartD
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• v.12D no.7 s.103
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• pp.1049-1064
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• 2005

The demands of increasingly complicated software have led to the proliferation of object-oriented design methodologies in embedded systems. To execute a system designed with objects in target hardware, a task set should be derived from the objects, representing how many tasks reside in the system and which task processes which event arriving at an object. The derived task set greatly influences the responsiveness of the system. Nevertheless, it is very difficult to derive an optimal task set due to the discrepancy between objects and tasks. Therefore, the common method currently used by developers is to repetitively try various task sets. This paper proposes Scenario-based Implementation Synthesis Architecture (SISA) to solve this problem. SISA encompasses a method for deriving a task set from a system designed with objects as well as its supporting development tools and run-time system architecture. A system designed with SISA not only consists of the smallest possible number of tasks, but also guarantees that the response time for each event in the system is minimized. We have fully implemented SISA by extending the ResoRT development tool and applied it to an existing industrial PBX system. The experimental results show that maximum response times were reduced $30.3\%$ on average compared to when the task set was derived by the best known existing methods.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.69-78
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• 2009

One of the most effective way to improve cache performance is to exploit both temporal and spatial locality given by any program executive characteristics. In this paper we present a high performance and low power cache structure with a bank selection mechanism that enhances exploitation of spatial and temporal locality. The proposed cache system consists of two parts, i.e., a main direct-mapped cache with a small block size and a fully associative buffer with a large block size as a multiple of the small block size. Especially, the main direct-mapped cache is constructed as two banks for low power consumption and stores a small block which is selected from fully associative buffer by the proposed bank selection algorithm. By using the bank selection algorithm and three state bits, We selectively extend the lifetime of those small blocks with high temporal locality by storing them in the main direct-mapped caches. This approach effectively reduces conflict misses and cache pollution at the same time. According to the simulation results, the average miss ratio, compared with the Victim and STAS caches with the same size, is improved by about 23% and 32% for Mibench applications respectively. The average memory access time is reduced by about 14% and 18% compared with the he victim and STAS caches respectively. It is also shown that energy consumption of the proposed cache is around 10% lower than other cache systems that we examine.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.3
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• pp.193-200
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• 2006

This paper suggests a 6-pulse-shift converter structure with PWM current-source inverter based on buck-boost configuration to improve the efficiency and to reduce the switching frequency of inverter for photovoltaic generation system, the device can be operated as interface system between solar module system and power system grid without energy storage cell. The circuit has six current-source buck-boost converter which operate chopper part and kas one full bridge inverter which make a decision the polarity of AC output. Therefore, the proposed PWM power inverter has advantages such as the reduction of witching loss and realization of unity power factor operation. The theoretical backgrounds are discussed and the input-output characteristics for the implemented prototype inverter using TMS320F2812 are verified experimentally in this paper.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.4
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• pp.393-409
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• 2003

In this paper, we present a multi-task debugging environment for Qplus-T embedded-system such as internet information appliances. We will propose the structure and functions of a remote multi-task debugging environment supporting environment effective ross-development. And, we are going enhance the communication architecture between the host and target system to provide more efficient cross-development environment. The remote development toolset called Q+Esto consists to several independent support tools: an interactive shell, a remote debugger, a resource monitor, a target manager and a debug agent. Excepting a debug agent, all these support tools reside on the host systems. Using the remote multi-task debugger on the host, the developer can spawn and debug tasks on the target run-time system. It can also be attached to already-running tasks spawned from the application or from interactive shell. Application code can be viewed as C/C++ source, or as assembly-level code. It incorporates a variety of display windows for source, registers, local/global variables, stack frame, memory, event traces and so on. The target manager implements common functions that are shared by Q+Esto tools, e.g., the host-target communication, object file loading, and management of target-resident host tool´s memory pool and target system´s symbol-table, and so on. These functions are called OPEn C APIs and they greatly improve the extensibility of the Q+Esto Toolset. The Q+Esto target manager is responsible for communicating between host and target system. Also, there exist a counterpart on the target system communicating with the host target manager, which is called debug agent. Debug agent is a daemon task on real-time operating systems in the target system. It gets debugging requests from the host tools including debugger via target manager, interprets the requests, executes them and sends the results to the host.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.75-84
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• 2005

This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small block size, a fully-associative spatial buffer with a large block size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically high performance and low power consumption comparing with any conventional NAND-type flash memory. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and average memory access time of the package module with smart buffer for a given buffer space (e.g., 3KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times(e.g., 32KB) as much space and a fully-associative configuration with twice as much space(e.g., 8KB)

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.4
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• pp.232-243
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• 2002

There are many methods for improving TLB (translation lookaside buffer) performance, such as increasing the number of entry in TLB, supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. So, we propose the new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two banked-TLB structures are integrated into a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also power consumption can be reduced by around 50% comparing with the fully associative TLB.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.28 no.2
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• pp.145-152
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• 2015

In the study, the effects of damping devices on damping ratio increase and wind-load reduction were investigated based on the computational platform, which is one of the parametric modeling methods. The computational platform helps the designers or engineers to evaluate the efficacy of the numerous alternative structural systems for irregular Super-Tall building, which is crucial in determining the capacity and the number of the supplemental damping devices for adding the required damping ratios to the building. The inherent damping ratio was estimated based on the related domestic and foreign researches conducted by using real wind-load records. Two types of damping devices were considered: One is inter-story installation type passive control devices and the other is mass type active control devices. The supplemental damping ratio due to the damping devices was calculated by means of equivalent static analysis using an equation suggested by FEMA. The optimal design of the damping devices was conducted by using the computational platform. The structural element quantity reduction effect resulting from the installation of the damping devices could be simply assessed by proposing a wind-load reduction factor, and the effectiveness of the proposed method was verified by a numerical example of a 455m high-rise building. The comparison between roof displacement and the story shear forces by the nonlinear time history analysis and the proposed method indicated that the proposed method could simply but approximately estimate the effects of the supplemental damping devices on the roof displacement and the member force reduction.