• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.45-52
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• 2002

In this contributions, we propose a new MSB(most significant bit) algorithm based on AOP(All One Polynomial) and two parallel semi-systolic architectures to computes $AB^2$over finite field $GF(2^m)$. The proposed architectures are based on standard basis and use the property of irreducible AOP(All One Polynomial) which is all coefficients of 1. The proposed parallel semi-systolic architecture(PSM) has the critical path of $D_{AND2^+}D_{XOR2}$ per cell and the latency of m+1. The modified parallel semi-systolic architecture(WPSM) has the critical path of $D_{XOR2}$ per cell and has the same latency with PSM. The proposed two architectures, PSM and MPSM, have a low latency and a small hardware complexity compared to the previous architectures. They can be used as a basic architecture for exponentiation, division, and inversion. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation. They can be used as a basic architecture for algorithms, such as the Diffie-Hellman key exchange scheme, the Digital Signature Algorithm(DSA), and the ElGamal encryption scheme which are needed exponentiation operation. The application of the algorithms can be used cryptosystem implementation based on elliptic curve.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.160-167
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• 2005

Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over $GF(2^{m})$ and it is computed by performing the repetitive $AB^{2}$ multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the $AB^2$ operation in GF$(2^{m})$. To obtain L×L digit-serial-in-serial-out architecture, new $AB^{2}$ algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about $(1/5)log_{2}(m+1)$, the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial $AB^{2}$ systolic architecture is approximately $10.9\%$ lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.143-152
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• 2012

In this paper hardware implementation of GF($2^{191}$) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF($2^m$), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.2
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• pp.70-81
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• 1998

This paper proposes an accurate and cost-effective COA defuzzifier of fuzzy logic controller (FLC). The accuracy of the proposed COA defuzzifier is obtained by involving both membership values and spans of membership functions in calculating a crisp value. The cost-effectiveness of the proposed COA defuzzifier is obtained by replacing the division in the COA defuzzifier by finding an equilibrium point of both the left and right moments. The proposed COA defuzzifier has two disadvantages that it ncreases the hardware complexity due to the additional multipliers and it takes a lot of computation time to find the moment equilibrium point. The first disadvantage is overcome by replacing the multipliers with the stochastic AND operations. The second disadvantage is alleviated by using a coarse-to-fine searching algorithm that accelerates the finding of moment equilibrium point. Application of the proposed COA defuzzifier to the truck backer-upper control problem is performed in the VHDL simulation and the control accuracy of the proposed COA defuzzifier is compared with that of the conventional COA defuzzifier in terms of average tracing distance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.6
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• pp.492-505
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• 2022

This study is a study on the results of improving the logic to effectively transmit and decode compressed data in real time by improving the encoding and decoding performance of BL-beta codes that can be used for lossless real-time transmission of IoT sensing data. The encoding process of BL-beta code includes log function, exponential function, division and square root operation, etc., which have relatively high computational burden. To improve them, using bit operation, binary number pattern analysis, and initial value setting of Newton-Raphson method using bit pattern, a new regularity that can quickly encode and decode data into BL-beta code was discovered, and by applying this, the encoding speed of the algorithm was improved by an average of 24.8% and the decoding speed by an average of 5.3% compared to previous study.

• The KIPS Transactions:PartA
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• v.12A no.2 s.92
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• pp.95-102
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• 2005

The Newton-Raphson iterative algorithm for finding a floating point reciprocal which is widely used for a floating point division, calculates the reciprocal by performing a fixed number of multiplications. In this paper, a variable latency Newton-Raphson's reciprocal algorithm is proposed that performs multiplications a variable number of times until the error becomes smaller than a given value. To find the reciprocal of a floating point number F, the algorithm repeats the following operations: '$'X_{i+1}=X=X_i*(2-e_r-F*X_i),\;i\in\{0,\;1,\;2,...n-1\}'$ with the initial value $'X_0=\frac{1}{F}{\pm}e_0'$. The bits to the right of p fractional bits in intermediate multiplication results are truncated, and this truncation error is less than $'e_r=2^{-p}'$. The value of p is 27 for the single precision floating point, and 57 for the double precision floating point. Let $'X_i=\frac{1}{F}+e_i{'}$, these is $'X_{i+1}=\frac{1}{F}-e_{i+1},\;where\;{'}e_{i+1}, is less than the smallest number which is representable by floating point number. So, $X_{i+1}$ is approximate to $'\frac{1}{F}{'}$. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation is derived from many reciprocal tables $(X_0=\frac{1}{F}{\pm}e_0)$ with varying sizes. The superiority of this algorithm is proved by comparing this average number with the fixed number of multiplications of the conventional algorithm. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a reciprocal unit. Also, it can be used to construct optimized approximate reciprocal tables. The results of this paper can be applied to many areas that utilize floating point numbers, such as digital signal processing, computer graphics, multimedia scientific computing, etc.

• Journal of the Korea Society of Computer and Information
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• v.19 no.7
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• pp.71-76
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• 2014

There is to be virtually impossible to solve the very large digits of prime number p and q from composite number n=pq using integer factorization in typical public-key cryptosystems, RSA. When the public key e and the composite number n are known but the private key d remains unknown in an asymmetric-key RSA, message decryption is carried out by first obtaining ${\phi}(n)=(p-1)(q-1)=n+1-(p+q)$ and then using a reverse function of $d=e^{-1}(mod{\phi}(n))$. Integer factorization from n to p,q is most widely used to produce ${\phi}(n)$, which has been regarded as mathematically hard. Among various integer factorization methods, the most popularly used is the congruence of squares of $a^2{\equiv}b^2(mod\;n)$, a=(p+q)/2,b=(q-p)/2 which is more commonly used then n/p=q trial division. Despite the availability of a number of congruence of scares methods, however, many of the RSA numbers remain unfactorable. This paper thus proposes an algorithm that directly and immediately obtains ${\phi}(n)$. The proposed algorithm computes $2^k{\beta}_j{\equiv}2^i(mod\;n)$, $0{\leq}i{\leq}{\gamma}-1$, $k=1,2,{\ldots}$ or $2^k{\beta}_j=2{\beta}_j$ for $2^j{\equiv}{\beta}_j(mod\;n)$, $2^{{\gamma}-1}$ < n < $2^{\gamma}$, $j={\gamma}-1,{\gamma},{\gamma}+1$ to obtain the solution. It has been found to be capable of finding an arbitrarily located ${\phi}(n)$ in a range of $n-10{\lfloor}{\sqrt{n}}{\rfloor}$ < ${\phi}(n){\leq}n-2{\lfloor}{\sqrt{n}}{\rfloor}$ much more efficiently than conventional algorithms.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.6
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• pp.221-228
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• 2013

It is impossible directly to find a prime number p,q of a large semiprime n = pq using Trial Division method. So the most of the factorization algorithms use the indirection method which finds a prime number of p = GCD(a-b, n), q=GCD(a+b, n); get with a congruence of squares of $a^2{\equiv}b^2$ (mod n). It is just known the fact which the area that selects p and q about n=pq is between $10{\cdots}00$ < p < $\sqrt{n}$ and $\sqrt{n}$ < q < $99{\cdots}9$ based on $\sqrt{n}$ in the range, [$10{\cdots}01$, $99{\cdots}9$] of $l(p)=l(q)=l(\sqrt{n})=0.5l(n)$. This paper proposes the method that reduces the range of p using information obtained from n. The proposed method uses the method that sets to $p_{min}=n_{LR}$, $q_{min}=n_{RL}$; divide into $n=n_{LR}+n_{RL}$, $l(n_{LR})=l(n_{RL})=l(\sqrt{n})$. The proposed method is more effective from minimum 17.79% to maxmimum 90.17% than the method that reduces using $\sqrt{n}$ information.