• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.39-43
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• 2009

In this paper, the flow characteristics of underfill material driven by capillary action between flip-chip and substrate were investigated. Also, the effects of viscosity level and dispensing point of underfill on flow characteristics were investigated. Flip chip package size was $5mm{\times}5mm{\times}0.65^tmm$, the diameter of solder bump was 100 ${\mu}m$, and the pitch was 150 ${\mu}m$. It was full grid area-array type with 1024 I/Os. The glass substrate was used and the gap between the chip and substrate was 50 ${\mu}m$. For the experimental study, three different underfills with different viscous properties($2000{\sim}3700$ cps), and two different types of dispensing methods(center dot and edge dot) were used. The flow characteristics and filling time of underfill were investigated by using CCD camera. The results show that the edge flow was faster than center flow due to the edge effect, which was caused by the resistance of solder bumps. In case of edge dot dispensing type, the filling time was faster due to the large edge effect, compared to center dot dispensing type. Also, it was found that the underfill flow was faster and the filling time decreased as the viscosity level of underfill was decreased.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.1
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• pp.47-54
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• 2021

For the bonding of smaller PCB solder bumps of less than 100 microns, an experiment was performed to make up a tin plating solution and find plating conditions in order to produce a bump pattern through tin electroplating, replacing the previous PCB solder bumps process by microballs. After SR patterning, a Cu seed layer was formed, and then, through DFR patterning, a pattern in which Sn can be selectively plated only within the SR pattern was formed on the PCB substrate. The tin plating solution was made based on methanesulfonic acid, and hydroquinone was used as an antioxidant to prevent oxidation of divalent tin ions. Triton X-100 was used as a surfactant, and gelatin was used as a grain refiner. By measuring the electrochemical polarization curve, the characteristics of organic additives in Triton X-100 and gelatin were compared. It was confirmed that the addition of Triton X-100 suppressed hydrogen generation up to -1 V vs. NHE, whereas gelatin inhibited hydrogen generation up to -0.7 V vs. NHE. As the current density increased, there was a general tendency that the grain size became finer, and it was observed that it became finer when gelatin was added.

• Journal of the Korean institute of surface engineering
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• v.33 no.2
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.1
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• pp.11-15
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• 2001

We present the design and strength evaluation of an anodically bonded pressurized cavity array, based on the energy release rate measured from the anodically bonded plates of two dissimilar materials. From a theoretical analysis, a simple fracture mechanics model of the pressurized cavity array has been developed. The energy release rate (ERR) of the bonded cavity with an infinite bonding length has been derived in terms of cavity pressure, cavity size, bonding length, plate size and material properties. The ERR with a finite bonding length has been evaluated from the finite element analysis performed for varying cavity and plate sizes. It is found that, for an inter-cavity bonding length greater than the half of the cavity length, the bonding strength of cavity array approaches to that of the infinite plate. For a shorter bonding length, however, the bonding strength of the cavity array is monotonically decreased with the ratio of the bonding length to the cavity length. The critical ERR of 6.21J/㎡ has been measured from anodically bonded silicon-glass plates. A set of critical pressure curves has been generated for varying cavity array sizes, and a design method of the pressurized cavity array has been developed for the failure-free wafer-level packaging of MEMS devices.

• Journal of Sensor Science and Technology
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• v.16 no.1
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• pp.62-67
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• 2007

This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin (Au/Sn) eutectic solder bonding. The membrane chip has 2.5 mm${\times}$2.5 mm, $0.5{\mu}m$ thick low stress silicon nitride membrane, 2 mm${\times}$2 mm Au/Ni/Cr membrane electrode, and $3{\mu}m$ thick Au/Sn layer. The backplate chip has 2 mm${\times}$2 mm, $150{\mu}m$ thick single crystal silicon rigid backplate, 1.8 mm${\times}$1.8 mm backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50-60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is $39.8{\mu}V/Pa$ (-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.130-130
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• 2003

일반적으로 Indium tin oxide (ITO)는 유기EL 소자 제작 공정에서 필수 불가결한 물질로 알려져 있다. ITO는 정공 수송의 기능을 하게 되는데 정공 주입의 효율을 향상시키기 위해서는 ITO 표면의 저 저항화와 ITO/유기박막 접합계면의 일함수 값의 적절한 균형이 중요하다. 그리고 현재 플라즈마를 이용한 ITO 기판의 세정은 산소 래디칼을 이용하여 표면을 산화하는 방식인 산소 플라즈마를 이용한 세정 방법이 널리 이용되고 있다. 본 연구에서는 ITO 표면의 탄소 오염물을 제거하여 저항특성을 향상시키기 위하여 원거리 산소와 수소 플라즈마 세정을 적용하였고, 그에 따른 탄소를 포함하는 오염물의 제거 효율과 산소와 수소 플라즈마로 처리된 ITO 표면의 특징을 기술하였다. 실험에 사용된 플라즈마 소스는 radio-frequency(RF) 플라즈마이고, 원거리 플라즈마 세정 시스템과 표면 분석 장비인 X-ray photoelectron spectroscopy(XPS)가 in-situ로 연결되어 있는 진공장비로 분석을 하였다 플라즈마 세정 전에 전처리 세정을 시행하지 알았으며, 세정 후 in-situ XPS에 의해서 화학 조성 및 결합 구조의 변화를 분석하였다. 또한 일함수와 면저항 값을 측정하고 그에 따른 표면의 저항 특성 및 표면 전위에 관하여 세정 효율과 연관지어 해석하였다. 원거리 산소/수소 플라즈마 세정 후 ITO 표면의 탄소오염물이 검출한계 이하로 효과적으로 제거된 것을 in-situ XPS 분석 결과로 확인하였고, 플라즈마 처리 순서 및 플라즈마 파워를 변화하여 그에 따른 표면의 결합 상태 및 화학 조성의 변화를 비교 분석하였다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1225_1226
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• 2009

유리 기판 상에 이중 게이트 절연막을 가지는 우수한 특성의 P형 엑시머 레이저 어닐링 (ELA) 다결정 실리콘 박막 트랜지스터를 제작하였다. 그리고 P형 짧은 채널 ELA 다결정 실리콘 박막 트랜지스터의 오프 상태 스트레스 하에서의 전기적 특성을 분석하였다. 스트레스하에서 긴 채널에서의 문턱 전압은 양의 방향으로 거의 이동하지 않는 (${\Delta}V_{TH}$ = 0.116V) 반면, 짧은 채널 박막 트랜지스터의 문턱 전압은 양의 방향으로 상당히 이동 (${\Delta}V_{TH}$ = 2.718V)하는 것을 확인할 수 있었다. 이런 짧은 채널 박막 트랜지스터에서 문턱 전압의 양의 이동은 다결정 실리콘 막과 게이트 산화막 사이의 계면에서의 전자 트랩핑 때문이다. 또한, 박막 트랜지스터의 누설 전류는 오프 상태 스트레스 하에서의 채널 영역의 홀 전하로 인하여 온 전류 수준을 감소시키지 않고 억제될 수 있었다. C-V 측정 결과는 계면의 전자 트랩핑이 드레인 접합 영역부근에서 발생한다는 것을 나타낸다.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.147-151
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• 1999

YBCO step-edge Josephson junction were fabricated on sapphire substrates. The steps were formed on R-plane sapphire substrates by using Ar ion milling with PR masks. The step angle was controlled in the wide range from 25$^{\circ}$ to 50$^{\circ}$ by adjusting both the Ar ion incident angle and the photoresist mask rotation angle relative to the incident Ar ion beam. CeO$_2$ buffer layer and in-situ YBa$_2Cu_3O_{7-{\delta}}$ (YBCO) thin films was deposited on the stepped R-plane sapphire substrates by pulsed laser deposition method. The YBCO film thickness was varied to obtain the ratio of film thickness to step height in the range from 0.5 to 1. The step edge junction exhibited RSJ-like behaviors with I$_cR_n$ product of 100 ${\sim}$ 300 ${\mu}$V, critical current density of 10$^3$ ${\sim}$ 10$^5$ A/ cm$^2$ at 77 K.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.83-86
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• 1999

We have fabricated $_2Cu_3O_7$ step-edge junctions with different step orientations and studied their transition properties. Steps with different orientations were prepared on the substrate. Josephson junctions were made on a single substrate with step orientations ranging from 0$^{\circ}$ to 165$^{\circ}$ at 15$^{\circ}$ interval. We measured current-voltage characteristics, the critical current, and the superconducting transition temperature as a function of the angle. The critical current showed a modulation that has a maximum near 0$^{\circ}$ or 90$^{\circ}$ and a minimum near 45$^{\circ}$ and 135$^{\circ}$. We believe that the critical current modulation with the step orientation could be associated with the symmetry of high T$_c$ superconductor.

• Korean Journal of Materials Research
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• v.12 no.6
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• pp.508-512
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• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.