• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.198-201
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• 2007

본 논문에서는 변형된 Newton-Raphson 알고리즘과 LUT(Look Up Table)를 사용하는 역제곱근 연산기를 제안한다. Newton-Raphson 부동소수점 역수 알고리즘은 일정한 횟수의 곱셈을 반복하여 역수 제곱근을 계산하는 방식이다. 변형된 Newton-Raphson 알고리즘은 하드웨어 구현에 적합하도록 변환되었으며, LUT는 오차를 줄이기 위해 개선되었다. 제안된 연산기는 LUT의 크기를 최소화하고, 순환적인 구조가 아닌 2-stage pipeline 구조를 가진다. 또한 IEEE-754 부동소수점 표준을 기초로 하는 24-bit 데이터 형식을 사용해 면적과 속도 향상에 유리하여 휴대용 기기의 멀티미디어 분야의 응용에 적합하다. 본 역제곱근 연산기는 소수점 이하 8-bit의 정확도를 가지며 VHDL을 이용하여 설계되었다. 그 크기는 $0.18{\mu}m$ CMOS 공정에서 약 4,000 gate의 크기를 보였으며 150MHz에서 동작이 가능하다.

• Journal of the KSME
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• v.56 no.9
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• pp.44-48
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• 2016

실제 크기의 로켓엔진은 수많은 예산이 소요되기 때문에 새롭게 설계된 엔진에 대하여 비행모델의 제작 및 실험연구는 예산과 위험성 때문에 매우 제한적으로 시행된다. 따라서 비행모델의 설계를 확정하기 위한 개발단계에서는 실제 크기의 로켓엔진의 특성을 나타낼 수 있는 소형 액체로켓을 제작하여 시험평가를 수행하게 된다. 이 글에서는 이러한 축소형 연소기 관련 연구동향을 알아보고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.61-70
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• 2008

Dynamic memory allocators are used for embedded systems to increase flexibility to manage unpredictable inputs and outputs. As embedded systems generally run continuously during their whole lifetime, fragmentation is one of important factors for designing the memory allocator. To minimize fragmentation, a budgeted memory allocator that has dedicated storage for predetermined objects is proposed. A budgeting method based on a mathematical analysis is also presented. Experimental results show that the size of the heap storage can be reduced by up to 49.5% by using the budgeted memory allocator instead of a state-of-the-art allocator. The reduced fragmentation compensates for the increased code size due to budgeted allocator when the heap storage is larger than 16KB.

• Journal of the Korean Society of Propulsion Engineers
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• v.13 no.1
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• pp.19-26
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• 2009

The response characteristics of $H_2O_2$ monopropellant thrusters at a pulse mode were presented in this paper. A catalyst bed was fixed to $MnO_2$/$Al_2O_3$ to investigate the thruster design effect to response time. Three different thrusters (50 N class) having different injectors, ullage volumes, catalyst grain sizes, and reactor volumes were prepared to investigate the response characteristics. As a result, the ignition delay, pressure rising and tail-off time of case 2-2 thruster with 16-20 mesh catalyst size were 14, 108, 94 ms respectively, which were comparable to requirement of response time at commercial hydrazine thrusters.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.10
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• pp.2639-2645
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• 2009

This paper describes a CPW oscillator using a spiral resonator. Spiral resonators are very useful in design CPW oscillators since they show a relatively higher Q than CPW hairpin and helical resonators. Prior to the design of oscillators, three CPW resonators are designed and compared. Electromagnetic (EM) simulation are performed for an improved design in design the CPW resonators and oscillators. Three oscillators are designed at 5.7 GHz using the mentioned CPW resonators. The measured output power of three CPW oscillators using the helical, hairpin, and spiral resonators are 2.55 dBm, 2.64 dBm, and 4.98 dBm, respectively. In addition, the size of three resonators are $102.15mm^2,\;130.05mm^2,\;80.625mm^2$, respectively, so it is proven that the proposed CPW oscillator using the spiral resonator has a smaller size than the others.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.133.1-133.1
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• 2014

이 발표에서 우리는 수백 나노미터 크기인 두 개의 나노 금속 원반 또는 나노 블록이 백 나노미터 이하의 간격으로 결합된 초미세 이중 금속 플라즈몬 광공진기를 제안하고 그 응용을 살펴본다. 원반구조 경우, 반지름이 476 nm인 나노원반 두 개가 100 nm 두께의 유전체 원반의 양쪽에 위치하여 1550 nm 공진파장을 가진 표면 플라즈몬 whispering-gallery-mode (WGM)을 유전체 내에 형성한다. 유전체의 두께를 일정하게 유지할 경우, WGM의 공진파장은 원반의 반지름에 따라 줄어든다. 반면, 반지름이 일정할 때에는 두 금속 원반 사이의 유전체 두께가 줄어듦에 따라 두 금속 원반 사이에 작용하는 표면 플라즈몬의 결합이 강해져서 공진파장이 길어진다. 따라서, 일반적으로 공진기의 크기가 줄어듦에 따라 공진파장이 짧아지는 것과 달리, 제안된 원반구조에서 발생하는 WGM는 원반의 반지름과 유전체의 두께를 함께 줄여도 공진파장이 동일하게 유지되는 차별화된 특성을 가지고 있다. 최종적으로 같은 공진파장을 가지는 WGM를 반지름 88 m, 유전체 두께 10 nm의 공진기에서도 여기시킬 수 있음으로, 모드부피(V)를 1/160으로 줄일 수 있다. 이에 비해, 공진모드의 품위값(Q)은 증가된 금속의 흡수손실에 의해 1/3정도 줄어듦으로써, 공진기와 물질의 상호작용 정도를 보여주는 Q/V값은 크기가 줄어든 공진기에서 오히려 50배 가량 증가함을 확인할 수 있다. 이 같은 초미세 플라즈몬 공진기는 매우 작은 굴절율 센서로서 응용을 가지고 있으며, 1160 nm/(단위 굴절율 변화)의 높은 민감도를 보인다. 한편, $200{\times}150{\times}100nm3$의 크기를 가진 두 개의 금속 나노블록이 10 nm의 공기 간격을 가지고 결합된 나노 공진기는, 공기 간격 내에 강하게 집적된 838 nm의 공진파장을 가진 플라즈몬 공진기 모드를 여기시킨다. 제안된 공진모드는 공기간격이 줄어듦에 따라 공진파장이 급격하게 증가하는 특성을 가지므로 옹스토롬 정도의 분해능을 가진 두께 변화 센서로 응용할 수 있다. 예를 들어, 공기간격 2 nm에서는 1A 두께 변화에 대해 공진파장 변화는 약 40 nm로 매우 민감하게 변화한다.

• Korean Chemical Engineering Research
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• v.55 no.6
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• pp.874-880
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• 2017

In this study, we performed numerical simulation of the adsorptive desulfurization reactor for a 100 kW fuel cell. Using experimental results and the adsorption kinetics theory, the adsorption rate of sulfur in diesel was estimated and verified by numerical analysis. By analyzing the performance of desulfurization according to reactor size, the optimal reactor size was determined. By maximizing processed diesel amount, optimal diesel flow rate was determined. Regeneration process was also confirmed for the obtained optimal reactor size. The present work will be utilized to design a diesel desulfurization reactor for a fuel cell used in a ship by further process modeling and economic analysis.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.4
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• pp.47-52
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• 2011

Nano-scale power splitter based on Si plasmonic waveguides are designed by utilizing the multimode interference (MMI) coupler. Effective dielectric method and longitudinal modal transmission-line theory are used for simulating the light propagation and optimizing the structural parameters at 3-D guiding geometry. The designed $1{\times}2$ 50:50 MMI power splitter has a nano-scale size of only $800nm{\times}850nm$. In order to achieve a variable power splitting ratio, a $2{\times}2$ MMI coupler is designed and the corresponding power splitting ratio can be tuned in the range of 78.5%:15.5%~5.5%:86.6%. Also, it is shown that it has a large bandwidth of $1.5{\mu}m{\sim}1.7{\mu}m$. In this range, the transmission is over 0.8.

• Journal of IKEEE
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• v.25 no.1
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• pp.180-192
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• 2021

One widely used algorithm for image recognition and pattern detection is the convolution neural network (CNN). To efficiently handle convolution operations, which account for the majority of computations in the CNN, we use hardware accelerators to improve the performance of CNN applications. In using these hardware accelerators, the CNN fetches data from the off-chip DRAM, as the massive computational volume of data makes it difficult to derive performance improvements only from memory inside the hardware accelerator. In other words, data communication between off-chip DRAM and memory inside the accelerator has a significant impact on the performance of CNN applications. In this paper, a simulator for the CNN is developed to analyze the main memory or DRAM access with respect to the size of the on-chip memory or global buffer inside the CNN accelerator. For AlexNet, one of the CNN architectures, when simulated with increasing the size of the global buffer, we found that the global buffer of size larger than 100kB has 0.8x as low a DRAM access count as the global buffer of size smaller than 100kB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.57-67
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• 2005

Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.