• The KIPS Transactions:PartC
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• v.11C no.2
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• pp.157-162
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• 2004

Recently, the growth of information infrastructure is getting fatter and faster. At the same time, the security accidents are increasing together. We have problem that do not handle traffic because we have the Intrusion Detection Systems in low speed environment. In order to overcome this, we need effective security analysis techniques that ran Processed data of high-capacity because high speed network environment. In this paper we proposed the Gigabit Intrusion Detection System for coordinated security function such as intrusion detection, response on the high speed network. We suggested the detection mechanism in high speed network environment that have pattern matching function based packet header and based packet data that is proceeded in system kernel area, we are shown that this mechanism was excellent until maximum 20 times than existing system in traffic processing performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.16-22
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• 2006

Gigabit transimpedance amplifiers are realihzed in submicron CMOS technologies for Gigabit Ethernet applications. The regulated cascode technique is exploited to enhance the bandwidth and noise performance simultaneously so that it can isolate the large input parasitic capacitance including photodiode capacitance from the determination of the bandwidth. The 1.25Gb/s TIA implemented in a 0.6um CMOS technology shows the measured results of 58dBohm transimpedance gain, 950MHz bandwidth for a 0.5pF photodiode capacitance, 6.3pA/sqrt(Hz) average noise current spectral density, and 85mW power dissipation from a single 5V supply. In addition, a 10Gb/s TIA is realized in a 0.18um CMOS incorporating the RGC input and the inductive peaking techniques. It provides 59.4dBohm transimpedance gain, 8GHz bandwidth for a 0.25pF photodiode capacitance, 20pA/sqrt(Hz) noise current spectral density, and 14mW power consumption for a single 1.8V supply.

• Journal of KIISE
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• v.43 no.7
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• pp.736-743
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• 2016

Several studies have reported the impact of core affinity on the network I/O performance of multi-core systems. As the network bandwidth increases significantly, it becomes more important to determine the effective core affinity. Although a framework for dynamic core affinity that considers both network and disk I/O has been suggested, the multiple queues provided by high-speed I/O devices are not properly supported. In this paper, we extend the existing framework of dynamic core affinity to efficiently support the multiple queues of high-speed I/O devices, such as 40 Gigabit Ethernet and NVM Express. Our experimental results show that the extended framework can improve the HDFS file upload throughput by up to 32%, and can provide improved scalability in terms of the number of cores. In addition, we analyze the impact of the assignment policy of multiple I/O queues across a number of cores.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9B
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• pp.883-891
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• 2009

This paper proposes Ethernet linear protection switching technology in order to provide the SONET/SDH-like resiliency over Metro Ethernet Networks. The proposed design is made of an architecture with a control processor board and several data processing boards, where the control processor board is independent of data processing board, providing a flexible solution for carrier Ethernet system. However, it leads an increasing message delay between inter-processors. In this paper, we implement and confirm a restoration of failed transport connections withing 50 millisecond in spite of increasing message delay between the control processing board and data processing board providing carrier-class network survivability.

• Journal of the Korea Convergence Society
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• v.8 no.8
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• pp.9-15
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• 2017

With the development of semiconductor integration technology, central processing units and storage devices have been miniaturized and performance has been rapidly developed, interconnection network technology is becoming a more important factor in terms of the performance of high performance computing system. In this paper, we analyze the trend of interconnection network technology used in high performance computing. Interconnect technology, which is the most widely used in the Supercomputer Top 500(2017. 06.), is an Infiniband. Recently, Ethernet is the second highest share after InfiniBand due to the emergence of 40/100Gbps Gigabit Ethernet technology. Gigabit Ethernet, where latency performance is lower than InfiniBand, is preferred in cost-effective medium-sized data centers. In addition, top-end HPC systems that demand high performance are devoting themselves from Ethernet and InfiniBand technologies and are attempting to maximize system performance by introducing their own interconnect networks. In the future, high-performance interconnects are expected to utilize silicon-based optical communication technology to exchange data with light.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.7
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• pp.413-420
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• 2006

The speed of present-day network technology exceeds a gigabit and is developing rapidly. When using TCP/IP in these high-speed networks, a high load is incurred in processing TCP/IP protocol in a host CPU. To solve this problem, research has been carried out into TCP/IP Offload Engine (TOE). The TOE processes TCP/IP on a network adapter instead of using a host CPU; this reduces the processing burden on the host CPU. In this paper, we developed two software-based TOEs. One is the TOE implementation using an embedded Linux. The other is the TOE implementation using Lightweight TCP/IP (lwIP). The TOE using an embedded Linux did not have the bandwidth more than 62Mbps. To overcome the poor performance of the TOE using an embedded Linux, we ported the lwIP to the embedded system and enhanced the lwIP for the high performance. We eliminated the memory copy overhead of the lwIP. We added a delayed ACK and a TCP Segmentation Offload (TSO) features to the lwIP and modified the default parameters of the lwIP for large data transfer. With the aid of these modifications, the TOE using the modified lwIP shows a bandwidth of 194 Mbps.

• Electronics and Telecommunications Trends
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• v.22 no.1 s.103
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• pp.51-58
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• 2007

인터넷의 발전과 더불어 네트워크 상에서의 침입 시도가 갈수록 증가되고 다변화됨으로써, 이에 대한 대응으로 많은 침입탐지시스템들이 개발되었다. 그러나, 현재의 대다수 침입탐지시스템들은 갈수록 증가하는 트래픽양을 처리하는 데 어려움이 있다. 즉, 기가비트 이더넷 환경과 같은 고속 네트워크 환경이 현실화되고 있고, 이를 바탕으로한 대용량의 데이터를 처리할 수 있는 보안 분석 기법들에 대한 필요성이 대두되고 있다. 따라서, 본 논문에서는 고속 네트워크 환경에 적합한 하드웨어 기반의 고성능 침입탐지 기술에 대해서 설명한다. 이는 대용량의 트래픽 데이터들을 실시간으로 분석하기위한 기술로써, 점점 고속화되고 대용량화되어 가는 대규모 네트워크 환경에서의 다양한 침입을 보다 빠르고 정확하게 탐지하고 대응하기 위한 기반을 제공한다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.799-802
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• 1998

As we know, gigabit ethernet is a new technology to be substituted for current fast ethernet used widely in local area network. The switch used in gigabit ethernet should deal with frames in giga-bps. To do such a fast switching, we need that serveral processes meet the budgets, such as MAC address table lookup, several giga speed path setup, fast scheduling, and etc. Especially MAC address table lookup has to be processed in the same speed with speed of incoming packets, thus the bottleneck in the process can cause packet loss by the overflow in the input buffer. We devise new practical hardware hashing method to perform fast table lookup by minimizing the number of external memory access and accelerating with hardware.

• 한국정보통신설비학회:학술대회논문집
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• 2003.08a
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• pp.240-243
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• 2003

본 논문에서는 Agere Systems사의 네트워크 프로세서를 사용한 고성능 IP-DiffServ/IP-MPLS 시스템의 구조를 제안하고 성능을 분석한다. 제안한 시스템은 기가비트 이더넷 뿐만 아니라 ATM과 POS 등 다양한 인터페이스를 제공하며 코어 및 에지 라우터로서 MPLS LER 또는 LSR로의 역할을 수행한다. 성능분석은 OPNET을 사용하여 시스템을 모델링한 후 입력 트래픽에 대해서 DiffServ 클래스별 지연시간과 지연의 주된 원인을 분석한다. 그리고 이를 바탕으로 시스템의 성능을 극대화할수 있는 네트워크 프로세서의 최적 파라메터를 도출한다. 성능분석 결과, 시스템이 각 서비스 클래스에 대해서 원활한 서비스를 제공하기 위해서는 프리미엄 서비스에는 최고의 우선순위를 부여하여 큐에 데이터 블럭들이 찰 때 마다. 즉시 서비스해 주어야 한다는 것을 알 수 있었다. 그리고 트래픽이 특정 출구 라인카드로 몰리는 핫스팟이 발생할 경우 트래픽의 지연이 증가하게되는데 이 지연의 주요 원인은 출구 라인카드에서의 큐잉에 의한 것임을 알 수 있었다.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.215-218
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• 2003

본 논문에서는 한국우주전파관측망(Korean VLBI Network; KVN)을 위해 현재 미국 MIT Haystack 천문대에서 개발되고 있는 천문관측 데이터를 위한 고속 대용량 저장장치에 대해 간략히 기술한다. 현재 개발중인 Mark 5 시스템은 하드디스크 기반의 Gbps VLBI 데이터 시스템이다. 주요 시스템은 낮은 가격의 PC 기반으로 8개의 탈부착이 가능한 ATA/IDE 형태의 하드디스크 뱅크를 두 개 가지며 1024Mbps 이상으로 고속기록 및 재생이 가능하다. 뿐만 아니라, Mark 5 시스템은 표준 기가비트 이더넷 연결을 통해 e-VLBI를 지원한다.