• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.35-39
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• 2011

Error correcting codes with easy variability in code rate and codeword length in addition to powerful error correcting capability are required for present and future mobile multimedia communication systems. And low complexity is also needed for the compact mobile terminals. In general, the irregular random LDPC(low-density parity-check) code is known to have the superior performance among various LDPC codes. But it has inefficiency since the various parity check matrices for various services should be stored for encoding and decoding. The structured LDPC codes which can easily provide various rates and lengths are studied recently. Therefore, the flexibility, memory size, and error performance of various structured LDPC codes are compared and analyzed in this paper. And the most appropriate structured LDPC code is also suggested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.123-129
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• 2006

In this paper, we concentrate on reducing the complexity for efficient encoder. We design structural LDPC code using circulant matrix and permutation matrix and eIRA code. It is possible to design low complex encoder by using shift register and differential encoder and interleaver than general LDPC encoder that use matrix multiplication operation. The code designed by this structure shows similar performance as random code. And the proposed codes can considerably reduce a number of XOR gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.14-19
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• 2006

The high encoding complexity of LDPC codes can be solved by designing structured parity-check matrix. If the parity-check matrix of LDPC codes is composed of same type of blocks, decoder implementation can be simple, this structure allow structured decoding and required memory for storing the parity-check matrix can be reduced largely. In this parer, we propose a construction algorithm for short block length structured LDPC codes based on girth condition, PEG algorithm and variable node connectivity. The code designed by this algorithm shows similar performance to other codes without structured constraint in low SNR and better performance in high SNR than those by simulation

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.773-776
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• 2001

열악한 전송 환경에서 고품질, 고신뢰성 통신을 지속적으로 하기 위해서 오류 정정 부호는 필수 적이다. 최근에 반복 복호를 통해 샤논의 채널 용량 한계에 근접하는 터보 부호와 LDPC부호가 가장 관심을 불러일으키고 있다. 반복 복호법은 성능 면에서는 우수해 지나 이에 따른 계산량 증가와 지연이 수반된다. 따라서 본 논문에서는 모의 실험을 통한 수신 데이터를 이용, SNR을 추정하여 LDPC 부호의 최대 반복 복호수에 따른 계산량과 지연을 효과적으로 줄일 수 있는 적응적 반복 복호수 설정 방식을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.207-213
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• 2006

In this paper, we reduce the computational complexity to find the minimum distance of RA codes by searching only valid codewords using repetition part. Since LDPC codes have repetition part like RA codes, we also apply this algorithm for computing the minimum distance of LDPC codes. The minimum distance dominates the code performance at high signal-to-noise ratios(SNRs) and in turn allows an estimate of the error floor. The proposed algorithm computes the minimum distance without any constraint on code structures. The minimum distances of LDPC codes and RA codes with large interleavers of practical importance are computed and used to obtain the error floor, which is compared with the performance of the iterative decoding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7C
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• pp.611-617
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• 2010

In this paper, we investigate the performances of the serial concatenated convolutional codes (SCCC) and low-density parity-check (LDPC) codes on perpendicular magnetic recording (PMR) channels. We discuss the performance of two systems when user bit-densities are 1.7, 2.0, 2.4 and 2.8, respectively. The SCCC system is less complex than LDPC system. The SCCC system consists of recursive systematic convolutional (RSC) codes encoder/decoder, precoder and random interleaver. The decoding algorithm of the SCCC system is the soft message-passing algorithm and the decoding algorithm of the LDPC system is the log domain sum-product algorithm (SPA). When we apply the iterative decoding between channel detector and the error control codes (ECC) decoder, the SCCC system is compatible with the LDPC system even at the high user bit density.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.1-8
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• 2005

In this paper, we present a novel LDPC code construction called as semi-algebra low density parity check(LDPC) codes which is one kind of deterministic LDPC code based on dual-diagonal sub-matrix. The constructing method results in a class of high rate LDPC codes. Codes in this class have a large girth and good minimum distances. Furthermore, they can be implemented by simple parallel array architecture using cyclic shift register and perform well with the iterative decoding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.287-294
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• 2010

MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.991-996
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• 2008

In this paper, we propose an LDPC-coded hybrid ARQ system using incremental redundancy and retransmission of a part of the transmitted packets. We also present a simple criterion for choosing two methods to support a desired throughput efficiently. Furthermore, we show that the throughput performance can be improved when multi-edge type LDPC codes with the structure of Raptor codes are employed for a hybrid ARQ scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.61-69
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• 2009

This paper presents the design results of a low complexity and high throughput LDPC encoder structure. In order to solve the high complexity problem of the LDPC encoder, a simplified matrix-vector multiplier is proposed instead of the conventional complex matrix-vector multiplier. The proposed encoder also adopts a partially parallel structure and performs column-wise operations in matrix-vector multiplication to achieve high throughput. Implementation results show that the proposed architecture reduces the number of logic gates and memory elements by 37.4% and 56.7%, compared with existing five-stage pipelined architecture. The proposed encoder also supports 800Mbps throughput at 40MHz clock frequency which is improved about three times more than the existing architecture.