• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2B
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• pp.263-271
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• 2004

In this paper, we proposed a new buffer management algorithm using perVC-Queuing discipline. Proposed algorithm uses service rate estimation and assigns dynamic perVC threshold to each VCs. Service rate estimation and dynamic perVC threshold combined with global threshold provide nearly optimal throughput and improve fairness performance of network resource among GFR VCs as well as guarantee MCR of all VCs. From simulation results, we demonstrate the proposed scheme fulfills the requirement of GFR service as well as improves the TCP throughput.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.101.1-101.1
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• 2010

$Cu(InGa)Se_2$ (CIGS) 태양전지는 박막형 태양전지 중 가장 높은 에너지 변환 효율이 보고 되고 있다. CIGS 태양전지를 제조하는 방법은 3 단계 동시 증착법, 금속 전구체의 셀렌화 공정법, 전기 증착법 등이 있다. 이 중 금속 전구체의 셀렌화 공정법은 다른 제조 방법에 비해 대면적 생산에 유리하고, 비교적 공정 과정이 간단하다는 장점이 있다. 하지만 금속 전구체의 미세구조 및 제조 방법, 셀렌화 공정의 최적화에 대한 연구가 부족하다. 본 실험에서는 후면전극으로 사용되는 Mo 층이 증착된 소다회 유리(soda-lime glass)를 기판으로 사용하였다. Cu-In(4:6), Cu-Ga(6:4) 타겟을 DC 스퍼터링 시스템을 이용하여 금속 전구체를 증착하였다. 이 후 미국 Delawere 대학교의 IEC 연구소와 한국전자통신연구원 (ETRI)에서 금속 전구체의 셀렌화 공정을 진행하였다. 셀렌화 공정 전후의 금속 전구체의 결정 크기와 미세구조의 변화를 관찰하기 위하여 주사전자현미경 (SEM)과 X선 회절 분석기 (XRD)를 사용하였다. 센렌화 공정이 진행된 금속 전구체 위에 버퍼층으로 사용되는 CdS와 전면전극으로 사영되는 ZnO, ITO 층을 합성한 후 에너지 변환 효율을 측정하였다. 최고 효율은 9.7%로 관찰되었다.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.3
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• pp.136-142
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• 2006

Existing buffer management schemes for shared-memory output queueing switches can be classified into two types: In the first type, some constant amount of memory space is guaranteed to each virtual queue using static queue thresholds. The static threshold method (ST) belongs to this type. On the other hand, the second type of approach tries to maximize the buffer utilization in 머 locating buffer memories. The complete sharing (CS) method is classified into this type. In the case of CS, it is very hard to protect regular traffic from mis-behaving traffic flows while in the case of ST the thresholds can not be adjusted according to varying traffic conditions. In this paper, we propose a new buffer management method called weighted dynamic thresholds (WDT) which can process packet flows based on loss priorities for quality-of-service (QoS) functionalities with fairly high memory utilization factors. We verified the performance of the proposed scheme through computer simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.8
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• pp.30-41
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• 2001

In this paper, the architecture of Dynamic GSMP V3(General Switch Management Protocol Version 3), an open interface protocol with resource management functions for efficient IP service on ATM over MPLS, is proposed and implemented in hardware. And we compare and analyze the proposed GSMP with the GSMP under standardization process in terms of CLR (Cell Loss Rate). We design the Slave block of the Dynamic GSMP V3 using SAM-SUNG SoG $0.5{\mu}m$ process, which performs functions for switch connection control in the ATM Switch. In order to compare difference performanaces between the proposed method and the conventional one, we conducts simulations using the minimum buffer search algorithm with random cell generation. The exponential results show that the proposed method leads to performance enhancement in CLR.

• Journal of the Korea Society for Simulation
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• v.22 no.3
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• pp.35-41
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• 2013

This paper applies an active period based bottleneck detection method to flow shop manufacturing system with limited buffer size. Manufacturing systems are constrained by one or more bottlenecks which degrades the system throughput. Conventional bottleneck detection methods include the waiting time or queue length of production stations and their utilization. Due to the random events such as production time of items, machine failure and repair times, the systems may change over time, and subsequently bottlenecks shift from one station to another station. Active period of working station may cause other stations to wait for productions. Information when and where active periods occur helps to find bottlenecks in production systems. Based on these informations, we predict bottlenecks in applying AweSim simulation language. We compare the simulation results of conventional methods with those obtained from duration of active period method, and duration ratio method of both sole and shift bottleneck periods. Even though simulation results are from simple flow shop model, they are quite promising for predicting bottlenecks of production stations. We hope this study aids in decision making regarding the improving system production yield and allocation of available resources of system.

• Journal of the Korea Society for Simulation
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• v.21 no.4
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• pp.11-24
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• 2012

We compared a DBR(drum-buffer-rope) system with a CONWIP(constant work-in-process) system in a production line with constant processing times. Based on the observation that a WIP-controlled line production system such as DBR and CONWIP is equivalent to a m-node tandem queue with finite buffer, we applied a max-plus algebra based solution method for the tandem queue to evaluate the performance of two systems. Numerical examples with 6 workstations were also used to demonstrate the proposed analysis. The mathematical analyses support that CONWIP outperforms DBR in terms of expected waiting time and WIP. Unlike the CONWIP case, sequencing workstations in a DBR affects the performance of the system. Delaying a bottleneck station in a DBR reduces expected waiting time.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.21-21
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• 2010

CIGS 박막 태양전지는 저가 기판의 사용, 원소재 소비가 적은 박막 증착, 연속공정 적용 등으로 인해 결정질 실리콘 태양전지에 비해 제조단가가 낮다. 변환효율의 경우 실험실 수준에서 최고 20%의 효율이 보고되고 있어 다결정 실리콘 태양전지와 견줄 만하다. 따라서 CIGS 박막 태양전지는 제조단가와 효율 면에서 매우 우수한 경쟁력을 가진 태양전지로 인식되고 있다. 일반적으로 CIGS 박막 태양전지는 Substrate/Mo전극/CIGS 광흡수층/CdS 버퍼층/ZnO 투명전극의 기본 구조를 가지고 있으며 다양한 공정과 디자인을 적용하여 제품이 생산되고 있다. 다양한 소재와 공정들 가운데에서 유리 소재를 기판으로 사용하면서 진공증발이나 스퍼터링과 같은 Physical Vapour Deposition(PVD)을 적용하여 CIGS 광흡수층을 제조하는 기술이 가장 보편적으로 적용되고 있다. 즉 상용화에 가장 근접해 있는 기술이라고 할 수 있으며 현재는 대량생산체제 구축을 위한 기술 개발이 진행되고 있다. 또한 종래의 기판소재와 광흡수층 제조 공정의 단점을 극복하기 위한 기술들도 개발되고 있다. 특히 유리 기판 소재를 금속이나 폴리머 소재를 대체하는 기술, PVD 공정이 아닌 비진공 공정을 적용하여 CIGS 광흡수층을 제조하는 기술 등은 응용성과 제조 단가 측면에서의 파급력이 크다고 할 수 있다. 본 발표에서는 저가 고효율 CIGS 박막 태양전지 개발을 위한 이슈들을 정리하고, 이를 해결하기 위한 국내외의 연구 개발 동향을 살펴보고자 한다. 또한 이를 바탕으로 하여 CIGS 박막 태양전지의 발전방향에 대해서 전망하고자 한다.