• School Mathematics
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• v.12 no.3
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• pp.371-388
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• 2010

The goals of this study are to inquire middle school students' understanding about prime number and to propose pedagogical implications for school mathematics. Written questionnaire were given to 198 Korean seventh graders who had just finished learning about prime number and prime factorization and then 20 students participated in individual interviews for member checks. In defining prime and composite numbers, the students focused on distinguishing one from another by numbering of factors of agiven natural number. However, they hardly recognize the mathematical connection between prime and composite numbers related on the multiplicative structure of natural number. This study suggests that it is needed to emphasize the conceptual relationship between divisibility and prime decomposition and the prime numbers as the multiplicative building blocks of natural numbers based on the Fundamental Theorem of Arithmetic.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.123-130
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• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.97-102
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• 2007

In this paper, a new architecture for fast-serial $GF(2^m)$ multiplier with low hardware complexity is proposed. The fast-serial multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the fast-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But The traditional fast-serial architecture needs extra (t-1)m registers for achieving the t times speed. In this paper a new fast-serial multiplier without increasing the number of registers is presented.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.3
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• pp.45-50
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• 2008

The choice of an irreducible polynomial and the representation of elements have influence on the efficiency of operators for finite fields. This paper suggests two serial multiplier for the extention field GF$(p^n)$ where p is odd prime. A serial multiplier using an irreducible binomial consists of (2n+5) resisters, 2 MUXs, 2 multipliers of GF(p), and 1 adder of GF(p). It obtains the mulitplication result after $n^2+n$ clock cycles. A serial multiplier using an AOP consists of (2n+5) resisters, 1 MUX, 1 multiplier of CF(p), and 1 adder of GF(p). It obtains the mulitplication result after $n^2$+3n+2 clock cycles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.24-26
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• 2022

시스톨릭 어레이는 DNN training 등 인공지능 연산의 대부분을 차지하는 행렬 곱셈을 수행하기 위한 하드웨어 구조로 많이 사용되지만, sparsity 가 높은 행렬을 연산할 때 불필요한 동작으로 인해 효율성이 크게 떨어진다. 본 논문에서 제안된 유동적 시스톨릭 어레이는 matrix condensing, weight switching, 그리고 direct output path 의 방법과 구조를 통해 sparsity 가 높은 행렬 곱셈의 수행 사이클을 줄일 수 있다. 시뮬레이션을 통해 기존 시스톨릭 어레이와 유동적 시스톨릭 어레이의 성능을 비교하였으며 8×8, 16×16, 32×32 의 크기를 가진 행렬을 동일 크기의 시스톨릭 어레이로 연산하였을 때 필요 사이클 수를 최대 12 사이클 절감할 수 있는 것을 확인하였다.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.861-864
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• 2001

많은 멀티미디어와 DSP 응용에서 입력과 출력 데이터 길이가 같은 고정 길이 곱셈기가 요구된다. 고정 길이 곱셈기는 확률적인 추정에 근거한 적절한 보상 바이어스를 더해줌으로써 일반적인 병렬 곱셈기와 비교하여 50%의 면적을 줄일 수 있다. 본 논문에서는 CSD 곱셈기에 적합한 고정길이 곱셈기의 구조를 제시하고 전파 캐리 선택절차를 이용한 부호확장제거방법과 결합함으로서 새로운 곱셈기구현 방안을 제시한다. 이 곱셈기의 응용으로서 SSB/BPSK-DS/CDMA 전송방식에 사용되는 힐버트 트랜스포머를 43탭 FIR 필터로 구현하고 기존의 compensation 벡터 방법과 비교하여 약 34%의 부호확장 오버헤드를 줄일 수 있음을 보인다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.3
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• pp.87-94
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• 2002

This study presents an MSB(Most Significant Bit) Int multiplier using cellular automata, along with a new MSB first multiplication algorithm over GF($2^m$). The proposed architecture has the advantage of high regularity and a reduced latency based on combining the characteristics of a PBCA(Periodic Boundary Cellular Automata) and with the property of irreducible AOP(All One Polynomial). The proposed multiplier can be used in the effectual hardware design of exponentiation architecture for public-key cryptosystem.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.762-763
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• 2016

In realizing a homomorphic encryption system, the operations of encrypt, decypt, and recrypt constitute major portions. The most important common operation for each back-bone operations include a polynomial modulo multiplication for over million-bit integers, which can be obtained by performing integer Fourier transform, also known as number theoretic transform. In this paper, we adopt and modify an algorithm for calculating big integer multiplications introduced by Schonhage-Strassen to propose an efficient algorithm which can save memory. The proposed architecture of number theoretic transform has been implemented on an FPGA and evaluated.