• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2347-2354
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• 2012

On Android environment, program development is conducted with JAVA SDK. However, using JAVA, it is operated over virtual machine which shows lower performance in terms of speed than traditional C language programming. The method writes program in C language, which conducts operation efficiently. In the paper, we implement multiplication using NDK and SDK to analyze the public key cryptography over Android environment. In case of SDK, we used BigInteger package and in case of NDK, we used Comb method. Moreover, execution time of arithmetic, branch and call operations over Android environment is compared to understand performance enhancement using NDK package.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.57-64
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• 2003

Recently, it has been shown that cryptographic devices such as smart cards are vulnerable to power attacks. In this paper, by mixing the randomization concept and the folding in half for secret scalar integer on ECCs, we propose an efficient and fast scalar multiplication algorithm to resist against simple power analysis(SPA) and differential power analysis(DPA) attacks. Our proposed algorithm as a countermeasure against SPA and DPA is estimated as a 33% speedup compared to the binary scalar multiplication.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.671-678
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• 2022

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.5
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• pp.1079-1087
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• 2018

Binary scalar multiplication which is the main operation of elliptic curve cryptography is vulnerable to the side-channel analysis. Especially, it is vulnerable to the side-channel analysis which uses power consumption and electromagnetic emission patterns. Thus, various countermeasures have been studied. However, they have focused on eliminating patterns of data dependent branches, statistical characteristic according to intermediate values, or the interrelationships between data. No countermeasure have been taken into account for the secure design of the key bit check phase, although the secret scalar bits are directly loaded during that phase. Therefore, in this paper, we demonstrate that we can extract secret scalar bits with 100% success rate using a single power or a single electromagnetic trace by performing key bit-dependent attack on hardware implementation of binary scalar multiplication algorithm. Experiments are focused on the $Montgomery-L{\acute{o}}pez-Dahab$ ladder algorithm protected by scalar randomization. Our attack does not require sophisticated pre-processing and can defeat existing countermeasures using a single-trace. As a result, we propose a countermeasure and suggest that it should be applied.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10a
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• pp.711-714
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• 2001

본 논문에서는 파이프라인 구조를 이용하여 고성능 1 차원 이산 웨이블렛 변환 필터를 설계하였다. 각 레벨에서 입력이 다운샘플링(downsampling, decimation)되므로 각 레벨의 하드웨어를 폴딩(folding) 기법을 이용하여 곱셈기와 덧셈기를 공유함으로써 복잡도를 개선하였다. 즉, 제안한 구조에서는 레벨 2 와 레벨 3 에서 폴딩된 구조의 C.S.R(Circular Shift Register)곱셈기와 덧셈기를 사용함으로써 하드웨어 효율(hardware utilization)을 각 레벨에서 100%로 높일 수 있다. 또한, 홀수와 짝수의 샘플을 병렬로 입력함으로써 단일 입력의 시스템과 비교할 때, 동일 시간에 병렬화 만큼의 이득을 얻을 수 있었고, 필터 계수는 미러 필터(mirror filter)의 특성을 이용하여 쳐대한 고역 필터(high pass filter)와 저역 필터(low pass filter)의 계수들을 공유함으로써 곱셈기와 덧셈기의 수를 반으로 줄였다. 그리고 임계 경로(critical path)를 줄이기 위한 파이프라인 레지스터를 삽입하여 고성능 시스템을 구현하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.123-129
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• 2008

In this paper, we propose the algorithm and circuit implementation to improve the performance of Multiplication using Addition based on H421 code. We expect that our method will be an essential element to make a embedded prototype in Ubiquitous environment.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1836-1842
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• 2010

Sensor network, which is technology to realize the ubiquitous environment, recently, could apply to the field of Mechanic & electronic Security System, Energy management system, Environment monitoring system, Home automation and health care application. However, feature of wireless networking of sensor network is vulnerable to eavesdropping and falsification about message. Presently, PKC(public key cryptography) technique using ECC(elliptic curve cryptography) is used to build up the secure networking over sensor network. ECC is more suitable to sensor having restricted performance than RSA, because it offers equal strength using small size of key. But, for high computation cost, ECC needs to enhance the performance to implement over sensor. In this paper, we propose the optimizing technique for multiplication, core operation in ECC, to accelerate the speed of ECC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.488-496
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• 2012

In this paper, the scheme for designing optimal beamforming matrix for interference control is proposed. The optimal beamforming matrix is found though linear combination of interference alignment conditions and renewal of linear combination coefficient. The proposed scheme has advantages that the complexity is reduced and there is no multiplying operation in matrix calculations even if proposed scheme has the form similar to that of existing least square based scheme. The simulation results show that proposed scheme has about 4bps/Hz higher gain than existing least square scheme. Also there is no additional multiplying calculation and increase of matrix size when the number of transmit and receive antennas is increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.67-74
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• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.