• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.4
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• pp.308-315
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• 2018

In this paper, we present the basic design results for high-resolution radar development at S-band frequency that can precisely measure the miss distance between two targets. The basic system requirement is proposed for the design of a 3.5 GHz linear frequency-modulated (LFM) radar with maximum detection distance and distance resolution of 2 km and 1 m, respectively, and the specifications of each module are determined using the radar equation. Our calculations revealed a signal-to-noise ratio ${\geq}30dB$ with a bandwidth of 150 MHz, transmission power of 43 dBm for the power amplifier, gain of 26 dBi for the antenna, noise figure of 8 dB, and radar cross-section of $1m^2$ at a target distance of 2 km from the radar. Based on the calculation results and the theory and method of LFM radar design, the hardware was designed using software defined radar technology. The results of the subsequent field test are presented that prove that the designed radar system satisfies the requirements.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.364-375
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• 2014

Parametric array transducers are used for long-range and highly directional communication in an underwater environments. The power amplifiers for parametric array transducers should have sufficient linear output characteristic and high efficiency to avoid communication errors, system heating, and fuel problems. But the conventional power amplifier with fixed source voltage is very low efficient due to large power loss by the big difference between the fixed source voltage and the amplifier output voltage. Thus to solve the problems this paper proposes the high efficiency power amplifier for parametric array transducers. The proposed power amplifier ensures high linearity of output characteristic by utilizing the push-pull class B type amplifier and furthermore gets high efficiency by applying the envelope tracking technique that variable source voltage tracks the envelope of the amplified signal. Also the paper suggests the detailed circuit topology and design guideline of class B push-pull type amplifier and variable output voltage AC/DC converter. Its characteristics are verified by the detailed simulation and experimental results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.9
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• pp.2227-2235
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• 2009

This paper describes the system configuration and measured performances of a wireless power transmission system which utilizes microwave. The technically final target of this system is to provide DC power to various mobile terminals within limited spaces such as buildings, conference rooms, and so on. The prototype system is built using in-house designed and fabricated circuits such as microwave oscillator, high power amplifier, microstrip patch antenna, low pass filter, and detector/rectifier. The fixed RF power of 29.3dBm at 2.4GHz is produced from the high power amplifier and transmitted through the transmitting antenna, while the received RF power at the receiving antenna is transformed into DC power through the detector/rectifier. The measured change of DC voltage according to the distance between transmitting and receiving antenna is described.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.127-132
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• 2018

In this paper, a high conversion gain cascode mixer was designed in W-band and verified by the fabrication and measurements. In the high frequency band such as a W-band, the conversion loss of a mixer is increased because of the poor performance of transistors. This high conversion loss of the mixer requires additional circuits which can give an extra gain such as an RF buffer amplifier, and this can affects the linearity and stability of the overall systems. Therefore, it is necessary to maximize the conversion gain of the mixer. To maximize the conversion gain of the mixer, biases of the transistor were optimized, and output load impedance was optimized by the load-pull simulations. The designed mixer was fabricated in $0.1-{\mu}m$ GaAs pHEMT technology and verified by the measurements. The measurement results shows a maximum conversion gain of -4.7 dB at W-band and an input 1-dB compression point of 2.5 dBm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10A
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• pp.922-929
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• 2005

This paper proposes an adaptive pilot beacon equipment for mobile communication systems based on direct spread spectrum technology which generates the pilot channel for handoff between base stations by using the information acquired from the downstream wireless signal regarding the overhead channel information. Such an adaptive pilot beacon equipment will enable low power operation since among the wireless signals, only the pilot channel will be generated and transmitted. The pilot channel in the downstream link of the CDMA receiver is used to acquire time and frequency synchronization and this is used to calibrate the offset for the beacon, which implies that time synchronization using GPS is not required and any location where forward receive signal can be received can be used as the installation site. The downstream link pilot signal searching within the CDMA receiver is performed by FPGA and DSP. The FPGA is used to perform the initial synchronization for the pilot searcher and DSP is used to perform the offset correction between beacon clock and base station clock. The CDMA transmitter the adaptive pilot beacon equipment will use the timing offset information in the pilot channel acquired from the CDMA receiver and generate the downstream link pilot signal synchronized to the base station. The intermediate frequency signal is passed through the FIR filter and subsequently upconverted and amplified before being radiated through the antenna.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.227-247
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• 2015

An X-band $8{\times}16$ dual-polarized active phased array antenna system has been implemented based on the substrate integrated waveguide(SIW) technology having low propagation loss, complete EM shielding, and high power handling characteristics. Compared with the microstrip case, 1 dB less is the measured insertion loss(0.65 dB) of the 16-way SIW power distribution network and doubled(3 dB improved) is the measured radiation efficiency(73 %) of the SIW sub-array($1{\times}16$) antenna element. These significant improvements of the power division loss and the radiation efficiency using the SIW, save more than 30 % of the total power consumption, in the active phased array antenna systems, through substantial reduction of the maximum output power(P1 dB) of the high power amplifiers. Using the X-band $8{\times}16$ dual-polarized active phased array antenna system fabricated by the SIW technology, the main radiation beam has been steered by 0, 5, 9, and 18 degrees in the accuracy of 2 degree maximum deviation by simply generating the theoretical control vectors. Performing thermal cycle and vacuum tests, we have found that the SIW array antenna system be eligible for the space environment qualification. We expect that the high efficiency SIW array antenna system be very effective for high performance radar systems, massive MIMO for 5G mobile systems, and various millimeter-wave systems(60 GHz WPAN, 77 GHz automotive radars, high speed digital transmission systems).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.1
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• pp.49-60
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• 2017

In this paper, we presented the result of the study on high-power handling capability of the X-band circular waveguide cavity filter configured at the output of high power amplifier(120 W) for geostationary satellites. The dual mode circular waveguide cavity filter with 6th order is selected and the physical model of the filter is designed after determination of the size of resonator from mode chart. Multipactor margin analysis is performed by the SEM method and the VMF method. The result shows that the VMF method predicts lower multipactor breakdown thresholds than the SEM method. Evaluating the multipactor margin obtained by the VMF method to ECSS criteria, we could decide to perform multipactor test. The multipactor test conducted in ESA facility shows that multipactor did not occur even until the RF power increased up to 540 W. In consequence, by both analysis and test, we could verify that the X-band circular waveguide cavity filter has the sufficient high-power handling capability to operate on orbit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.