• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1537-1545
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• 1993

In this paper, we design a pattern generator and a fault position detector to implement the proposed fault test algorithms which are Column Weight Sensitive Fault (CWSF) test algorithm and bit line decoder fault test algorithm for performing the Built-In Self Test(BIST) in RAM. A pattern generator consists of an address generator and a data generator. An address generator is divided into a row address generator for effective address and a column address generator for sequential and parallel addresses. A fault position detector is designed to determine whether full occurred or not and to find the position of the fault. We verify the implemented circuits by the simulation.

• Electrical & Electronic Materials
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• v.10 no.4
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• pp.349-354
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• 1997

This paper aims at studying the improvement of test method for t-weight sensitive fault (t-wsf) detect. The development of RAM fabrication technology results in not only the increase at device density on chips but also the decrease in line widths in VLSI. But, the chip size that was large and complex is shortened and simplified while the cost of chips remains at the present level, in many cases, even lowering. First of all, The testing patterns for RAM fault detect, which is apt to be complicated , need to be simplified. This new testing method made use of Local Lower Bound (L.L.B) which has the memory with the beginning pattern of 0(l) and the finishing pattern of 0(1). The proposed testing patterns can detect all of RAM faults which contain stuck-at faults, coupling faults. The number of operation is 6N at 1-weight sensitive fault, 9,5N at 2-weight sensitive fault, 7N at 3-weight sensitive fault, and 3N at 4-weight sensitive fault. This test techniques can reduce the number of test pattern in memory cells, saving much more time in test, This testing patterns can detect all static weight sensitive faults and pattern sensitive faults in RAM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1205-1214
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• 2004

For tile physical defects occurring in CMOS circuits which are not handled well by voltage-based testing, current testing is remarkable testing technique. Fault models based on defects must accurately describe the behaviour of the circuit containing the defect. In this paper, An efficient collapsing algorithm for fault models often used in current testing is proposed. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults that have to be considered by fault collapsing and its usefulness in various current based testing models.

• Journal of the Korea Society of Computer and Information
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• v.16 no.3
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• pp.141-147
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• 2011

This paper proposes an efficient two-stage fault prediction algorithm for fault detection and diagnosis of induction motors. In the first phase, we use a linear predictive coding (LPC) method to extract fault patterns. In the second phase, we use a dynamic time warping (DTW) method to match fault patterns. Experiment results using eight vibration data, which were collected from an induction motor of normal fault states with sampling frequency of 8 kHz and sampling time of 2.2 second, showed that our proposed fault prediction algorithm provides about 45% better accuracy than a conventional fault diagnosis algorithm. In addition, we implemented and tested the proposed fault prediction algorithm on a testbed system including TI's TMS320F2812 DSP that we developed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.12-18
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• 1974

In this paper, we are concerned with the problem of generating fault-detection experiment for combinational logic networks with fan-out. We establish the lower limit on the necessary number of fault-section tests and show how such experiments can be obtained by considering inversion parity from the output to the point whore fan-out exilts on the networks. Boolean difference is used advantageously.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.2
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• pp.70-76
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• 1984

In this paper, a functional m-redundant system, which is m-fault tolerant, is defined based on the graph-theory. This system is designed to be t(t$\geq$m) fault-diagnosable by comparing its unit's outcomes without additive test functions, so, the system down for diagnosis is not needed. The diagnostic model for this system is presented. It is to avail the redundancy of the system effectively. It is shown that this model can be converted into Preparata's model. Thus, the diagnostic characteristics of a functional m-redundant system is analyzed by the method originated by Preparata et al.

• Proceedings of the Korean Reliability Society Conference
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• 2011.06a
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• pp.163-171
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• 2011

본 논문에서는 LED 패키지 내부 이종물질간의 열팽창계수 차에 의한 박리 현상 및 이에 따른 LED 광속저하 메커니즘의 규명에 대한 연구를 진행하였다. 친환경 조명의 대두 및 고휘도 White LED의 급속적인 발전과 개발에 따라 LED 패키지 고장 형태가 점점 줄어드는 추세이기는 하나, 여전히 실사용 환경에서는 LED 패키지의 고장이 다양한 형태로 발생되고 있는 것이 실정이다. 이 중 LED 패키지 내부 이종물질간의 박리에 의한 고장은 LED 발광효율을 감소시키는 형태로 발생되고, 이에 대한 영향을 최소화하기 위하여 LED 패키지 제조업체 및 다수의 연구소에서 많은 노력을 기울이고 있다. 대표적인 박리 검사방법으로는 잉크침투 테스트 방법을 보편적으로 사용하고 있으나, 이 방법은 시료의 파손 및 검사 시간이 24시간이상 소요된다는 단점을 가지고 있다. 이에 본 논문에서는 헬륨 가스를 사용하여 LED 패키지 박리 유무를 검출해 내는 평가법을 제시하였고, 이 방법을 통하여 시료 파손 없이 짧은 시간 안에 박리 유무를 평가할 수 있음을 확인 할 수 있었다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.29-30
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• 2018

전 세계적으로 급증하고 있는 에너지 수요로 인해 오일, 가스 등의 에너지 생산 매체를 운송 할 수 있는 수송 수단인 배관에 대한 수요도 증가하고 있는 추세이다. 그러나 이러한 배관을 장시간 사용할 경우 노후화로 인해 발생되는 파공은 배관에 흐르는 유체 누설의 원인이 되고, 나아가서 경제 및 재난 피해를 야기할 수 있다. 따라서 다양한 배관 누설 검출 기술들이 개발되고 있는 추세이며, 이를 위해서는 신뢰성 있는 결함 모사 데이터의 확보가 매우 중요하다. 본 논문에서는 신뢰성 있는 데이터 수집을 위해 배관의 누설 상황을 모사 할 수 있는 테스트베드를 제어하고, 테스트베드에서 데이터를 안정적으로 취득할 수 있는 테스트베드 제어 및 데이터 취득 시스템을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.24-33
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• 2002

For mixed signal circuits that integrate both analog and digital blocks onto the same chip, testing the mixed circuits has become the bottleneck. Since most of mixed signal circuits are functionally tested, mixed signal testing needs expensive automatic test equipments for test input generation and response acquisition. In this paper, a new efficient BIST is developed which can be used for mixed signal circuits. In the new BIST, only faults on embedded resistances, capacitances and its combinations are considered. To guarantee the quality of chips, the new BIST performs both voltage testing and phase testing. Using these two testing modes, all the faults are detected. In order to support this technique, the voltage detector and the phase detector are developed. Experimental results prove the efficiency of the new BIST.

• The Journal of Information Technology
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• v.3 no.3
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• pp.57-65
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• 2000

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.