• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.443-447
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• 2005

The SAR measurement system with stationary probes, presented in this paper, can calculate area SAR value based ell the measured 9 electric field data. By converting obtained area SAR to the volume SAR, the results can be acquired in a few seconds. The system can be very useful tool in the stages of handset development for mobile communication as well as in the handset production line because of its rapid SAR measurement. The system showed good linearity characteristics at 835 MHz of 10 $\sim$ 27 dBm input power range.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.30 no.1
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• pp.75-86
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• 2012

Synthetic Aperture Radar(SAR) imaging system is independent of solar illumination and weather conditions; however, SAR image is difficult to interpret as compared with optical images. It has been increased interest in multi-sensor fusion technique which can improve the interpretability of $SAR^{\circ\circ}$ images by fusing the spectral information from multispectral(MS) image. In this paper, a multi-sensor fusion method based on high-frequency extraction process using Fast Fourier Transform(FFT) and outlier elimination process is proposed, which maintain the spectral content of the original MS image while retaining the spatial detail of the high-resolution SAR image. We used TerraSAR-X which is constructed on the same X-band SAR system as KOMPSAT-5 and KOMPSAT-2 MS image as the test data set to evaluate the proposed method. In order to evaluate the efficiency of the proposed method, the fusion result was compared visually and quantitatively with the result obtained using existing fusion algorithms. The evaluation results showed that the proposed image fusion method achieved successful results in the fusion of SAR and MS image compared with the existing fusion algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1747-1754
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• 2016

This paper presents a high accuracy and fast hybrid on-chip temperature sensor. The proposed temperature sensor combines a SAR type temperature sensor with a ${\Sigma}{\Delta}$ type temperature sensor. The SAR type temperature sensor has fast temperature searching time but it has more error than the ${\Sigma}{\Delta}$ type temperature sensor. The ${\Sigma}{\Delta}$ type temperature sensor is accurate but it is slower than the SAR type temperature sensor. The proposed temperature sensor uses both the SAR and ${\Sigma}{\Delta}$ type temperature sensors, so that the proposed temperature sensor has high accuracy and fast temperature searching. Also, the proposed temperature sensor includes a temperature error compensating circuit by storing the temperature errors in a memory circuit after chip fabrication. The proposed temperature sensor was fabricated in 3.3V CMOS $0.35{\mu}m$ process. Its temperature resolution, power consumption, and area are $0.15^{\circ}C$, $540{\mu}W$, and $1.2mm^2$, respectively.

• Journal of the Korean Society of Radiology
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• v.17 no.7
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• pp.1133-1138
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• 2023

This study analyzed the relationship between image parameters and specific absorption rate (SAR) in various sequence environments to optimize SAR. For this purpose, image parameters were adjusted for T2, T1, STIR, T1 FLAIR, and T2 FLAIR sequences in a 3.0T MRI, and the whole body (WB) SAR and head SAR calculated by the device were measured. Then, the SAR was evaluated by adjusting the number of images and the flip angle (FA) of the refocusing RF. As a result, SAR increased as the number of image increased in all sequences. T1 and T1 FLAIR had correlation coefficients (r) of 0.876, 0.876 (WB SAR, head SAR), 0.867, 0.867 (WB SAR, head SAR), respectively, and STIR had the highest correlation with 0.898 and 0.899 (WB SAR, head SAR). showed (p<0.05). When applied by increasing the refocusing FA, WB SAR and head SAR increased overall in all sequences. The T1 and T2 sequences showed high correlation with correlation coefficients (r) of 0.897, 0.898 (WB SAR, head SAR) and 0.914, 0.915 (WB SAR, head SAR), respectively, while the sequences to which the inversion recovery technique was applied had relatively low FA, showed less sensitivity to increase. Therefore, in a sequence with a relatively low TR, minimizing the number of image and applying the fast spin echo to reduce the refocusing FA in a sequence with a high duty cycle are effective in reducing SAR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• Journal of IKEEE
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• v.25 no.4
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• pp.634-643
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• 2021

In this paper, an FPGA-based acceleration scheme of range Doppler algorithm (RDA) is proposed for the real time synthetic aperture radar (SAR) imaging. Hardware architectures of matched filter based on systolic array architecture and a high speed sinc interpolator to compensate range cell migration (RCM) are presented. In addition, the proposed hardware was implemented and accelerated on Xilinx Alveo FPGA. Experimental results for 4096×4096-size SAR imaging showed that FPGA-based implementation achieves 2 times acceleration compared to GPU-based design. It was also confirmed the proposed design can be implemented with 60,247 CLB LUTs, 103,728 CLB registers, 20 block RAM tiles and 592 DPSs at the operating frequency of 312 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.