• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.832-834
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• 2004

미래의 인터넷이 저속 네트워크에서 고속 네트워크로 그 특성이 변하고 있음에 반해 비교적 저속 네트워크에 최적화된 TCP의 성능 개선은 이루어지지 않고 있어 이래 인터넷에서 TCP의 효율적인 동작을 보장하기 어려운 실정이다. 이를 위해 본 논문에서는 기존 AIMD 메커니즘을 수정한 HSTCP와 네트워크로부터 명확한 피드백을 요하는 새로운 프로토콜인 XCP에 대해 살펴보고 고속 네트워크에 적합한 개선된 HSTCP 메커니즘을 제안한다.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1429-1432
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• 2000

본 논문은 Grafcet[1]을 이용하여 고속전철 승강문 제어를 실행하기 위한 운영 모드에 대해 논의한다. 고속전철에 사용하는 승강문 제어 관련 동작 상태의 정의 및 제어 조건[2]을 인용하여 승강문 제어를 위한 기본 사양 및 운영자 요구사양을 정의한 다음, 열차편성을 1개의 동력차와 4개의 객차로 가정한 후, 이에 대한 승강문 운영 모드 관련 순차 프로그램을 Grafcet 을 이용하여 구성하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1582-1589
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• 2000

A dynamic D-flipflop is proposed aiming at low power and high frequency(GHz) operations. The proposed D-flipflop uses a smaller number of pmos transistors that it operates high speed in same dimensions. Also, it consumes lower power than conventional approaches by a shared nmos with clock input. In order to compare the performance of the proposed D-flipflop, we perform simulation estimating power consumption and maximum operating frequency of each same dimension D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop is evaluated via the same method. The simulation results show that the proposed D-fliplflop has good performance than conventional circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.

• 전기의세계
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• v.37 no.4
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• pp.58-70
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• 1988

이하에서는 자기부상철도의 기본적인 동작원리와 특징, 개발 및 실용의 현상, 고속 시스템의 실용화의 전망, 종래의 철차륜, 철레일 방식의 철도와 비교했을 경우의 특징등에 대해서 설명한다.

• The Magazine of the IEIE
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• v.24 no.6
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• pp.98-106
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• 1997

• Journal of KIISE
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• v.41 no.12
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• pp.1050-1057
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• 2014

Electroencephalogram (EEG)-based brain-computer interfaces (BCI) can be used for a number of purposes in a variety of industries, such as to replace body parts like hands and feet or to improve user convenience. In this paper, we propose a method to decompose and extract motor imagery EEG signal using Empirical Mode Decomposition (EMD) and Fast Fourier Transforms (FFT). The EEG signal classification consists of the following three steps. First, during signal decomposition, the EMD is used to generate Intrinsic Mode Functions (IMFs) from the EEG signal. Then during feature extraction, the power spectral density (PSD) is used to identify the frequency band of the IMFs generated. The FFT is used to extract the features for motor imagery from an IMF that includes mu rhythm. Finally, during classification, the Support Vector Machine (SVM) is used to classify the features of the motor imagery EEG signal. 10-fold cross-validation was then used to estimate the generalization capability of the given classifier., and the results show that the proposed method has an accuracy of 84.50% which is higher than that of other methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.90-97
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• 2006

In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.439-446
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• 2004

This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91㏈ with a input frequency of 103MHz at 500Msample/s and consumes 203㎽ with a 1.8V single power supply. The chip is designed with a 0.18mm 1-poly 6-metal CMOS technology and occupies active area of 760${\mu}{\textrm}{m}$*800${\mu}{\textrm}{m}$.