• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.101-108
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• 2007

Parallel processing algorithms, coupled with advanced networking and distributed computing architectures, improve the overall computational performance, dependability, and versatility of a digital signal processing system In this paper, novel parallel algorithms are introduced and investigated for advanced sonar algorithm, conventional matched-field processing (CMFP). Based on a specific domain, each parallel algorithm decomposes the sequential workload in order to obtain scalable parallel speedup. Depending on the processing requirement of the algorithm, the computational performance of the parallel algorithm reveals different characteristics. The high-complexity algorithm, CMFP shows scalable parallel performance on the array of DSP processors. The impact on parallel performance due to workload balancing, communication scheme, algorithm complexity, processor speed, network performance, and testbed configuration is explored.

• Korean Journal of Optics and Photonics
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• v.5 no.1
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• pp.144-151
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• 1994

We designed and fabricated a $2{\times}4$ symmetric self electro-optic effect device array using GaAs/ AIo.04 G$\DeltaR$), and optical bistability loop width ($\Delta$). The average values of the elements of the $2{\times}4$ S-SEED array were CR~13.1, R~24%, and $\Delta$~91%. It was found that the AFP cavity structure enhances the self-biased optical bistability in ESQW-SEED under no external bias. That is due to the decreased intrisic region thickness in AFP-SEED structures, and which increases the built-in electric fields. The zero-biased S-SEED showed CR of ~4.7, R~9%, and $\Delta$~22%.X>~22%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.30-36
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• 2009

Various types of ultra-wideband components with 10's of GHz bandwidth have been developed utilizing a uniplanar ultra-wideband balun, which is a simple microstrip-to-coplanar stripline (CPS) transition structure with the operating frequency range from near DC to over 40 GHz. Developed ultra-wideband components include antennas, mixers, doublers, and detectors in a carrier type and in a surface mountable type. One of surface mountable components, for example, single balanced doubler has output frequency 8 ~ 28 GHz. These high-Performance, low-cost ultra-wideband components may replace expensive conventional components, and also can be used to develop new multi-GHz OWE application areas.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.2
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• pp.33-44
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• 2010

This paper propose the structure of real-time face detection hardware architecture for robot vision processing applications. The proposed architecture is robust against illumination changes and operates at no less than 60 frames per second. It uses Modified Census Transform to obtain face characteristics robust against illumination changes. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data, and finally detected the face using this data. This paper describes the face detection hardware structure composed of Memory Interface, Image Scaler, MCT Generator, Candidate Detector, Confidence Comparator, Position Resizer, Data Grouper, and Detected Result Display, and verification Result of Hardware Implementation with using Virtex5 LX330 FPGA of Xilinx. Verification result with using the images from a camera showed that maximum 32 faces per one frame can be detected at the speed of maximum 149 frame per second.

• Journal of Broadcast Engineering
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• v.25 no.4
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• pp.528-536
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• 2020

As humanoid robot technology advances, the use of robots for performance is increasing. As a result, studies are being conducted to increase the scope of use of robots in performances by making them natural like humans. Among them, the use of motion capture technology is often used, and there are environmental inconveniences in preparing for motion capture, such as the need for IMU sensors or markers attached to each part of the body and precise high-performance cameras. In addition, for robots used in performance technology, there is a problem that they have to respond in real time depending on the unexpected situation or the audience's response. To make up for the above mentioned problems, in this paper, we proposed a real-time motion capture system by using a number of RGB-D cameras and creating natural robot motion similar to human motion by using motion-captured data.

• KIISE Transactions on Computing Practices
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• v.20 no.10
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• pp.525-533
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• 2014

SCST(The generic SCSI target subsystem for Linux) enables developers to make SCSI target storage and supports various SCSI network protocol such as iSCSI, FC, SRP. In this paper, we propose storage virtualization method using SCST and virtualize all flash array as high performance storage through 4Gb Fiber Channel, 10Gb Ethernet and 40Gb Infiniband and evaluate their performance, respectively. Experimental result shows that 40Gb infiniband network appliance have better performance than others. In case of sequential/random read, 40Gb infiniband network appliance shows 78% and 79% of local all flash array performance attached to SCSI target system. In case of sequential/random write, it shows 83% and 88% of local flash array performance attached to SCSI target system.

• Journal of KIISE:Software and Applications
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• v.35 no.5
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• pp.281-287
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• 2008

Data transfers occur during the execution time of a Java program, from constant to variable, from variable to other variable and so on. Data are located in memory and hence data transfer requires access to memory. As memory access generates both time delay and energy consumption it is absolutely necessary to know the data transfer overheads incurred among different paths not only to write an efficient program but also to build a high-performance Java virtual machine. In this paper we classify Java memory into three different regions, constant, local variable, and field, and then investigate data transfer overheads among these regions. The result says that the transfer between local variables incur the least overhead usually, while the transfer between fields incur the most. The difference of overheads reaches up to a double. Optimization techniques like JIT reduces the data transfer overhead dramatically. It is observed that the overhead is reduced from 14 to 27 times for the case of Hotspot JVM.

• Journal of Broadcast Engineering
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• v.16 no.3
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• pp.403-415
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• 2011

In this paper, we proposed a hardware architecture to generate digital holograms at high speed. It used the modified computer-generated hologram (CGH) algorithm and adapted the pipeline-based hardware to be able to remove memory bottleneck problem. It uses not the method which generates a hologram by accumulating intermittent holograms but the one which independently generates a pixel of a final hologram and uses the appropriate CGH algorithm for the selected method. Based on the CGH algorithm we proposed the architecture of the digital hologram generator which consists of input interface part, calculating part, and normalizing part. The hardware can decrease memory usage because it repeatedly use object light sources which is stored in the internal buffer. It is also operationally parallelized by vertically adding unit cells. It can generate 86 frames of HD digital hologram per 1 second for 1K light sources.