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A New Architecture of High-Performance Digital Hologram Generator based on Independent Calculation of a Holographic Pixel

독립적 홀로그램 화소 연산 방식의 고성능 디지털 홀로그램 생성기의 하드웨어 구조

  • Lee, Yoon-Huyk (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Seo, Young-Ho (College of Liberal Arts, Kwangwoon University) ;
  • Choi, Hyun-Jun (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Kim, Dong-Wook (Department of Electronic Materials Engineering, Kwangwoon University)
  • Received : 2011.03.16
  • Accepted : 2011.05.11
  • Published : 2011.05.30

Abstract

In this paper, we proposed a hardware architecture to generate digital holograms at high speed. It used the modified computer-generated hologram (CGH) algorithm and adapted the pipeline-based hardware to be able to remove memory bottleneck problem. It uses not the method which generates a hologram by accumulating intermittent holograms but the one which independently generates a pixel of a final hologram and uses the appropriate CGH algorithm for the selected method. Based on the CGH algorithm we proposed the architecture of the digital hologram generator which consists of input interface part, calculating part, and normalizing part. The hardware can decrease memory usage because it repeatedly use object light sources which is stored in the internal buffer. It is also operationally parallelized by vertically adding unit cells. It can generate 86 frames of HD digital hologram per 1 second for 1K light sources.

본 논문에서는 고속으로 디지털 홀로그램을 생성할 수 있는 하드웨어구조를 제안하였다. 수정된 컴퓨터 생성 홀로그램(computer-generated hologram, CGH) 알고리즘을 이용하고, 기존의 한 화소에 대한 홀로그램 전체 화소를 연산하는 방법이 아니라 객체 전체 화소에서 홀로그램의 한 화소씩 연산하는 방법을 선택하여 홀로그램 한 화소씩 계산하고 바로 출력 하여 메모리 병목 현상을 제거하기 위한 파이프라인 기반의 하드웨어 구조를 제안하였다. CGH 알고리즘을 바탕으로 입력부, 연산부, 및 정규화부로 구성된 디지털 홀로그램 생성기의 구조를 제안하였고, 이를 효율적인 하드웨어로 구현하였다. 객체의 화소만 저장하여 반복 사용하기 때문에 메모리의 사용량을 줄일 수 있었다. 제안한 하드웨어는 세로 방향으로 확장을 하여 동작을 병렬화시킬 수 있다. 제안한 하드웨어는 1K의 광원에 대해 HD급 홀로그램을 초당 약 87장을 생성할 수 있었다.

Keywords

References

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