Design Optimization of the Arithmatic Logic Unit Circuit for the Processor to Determine the Number of Errors in the Reed Solomon Decoder (리드솔로몬 복호기에서 오류갯수를 계산하는 처리기의 산술논리연산장치 회로 최적화설계)
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- The Journal of Korean Institute of Communications and Information Sciences
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- v.36 no.11C
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- pp.649-654
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- 2011