• Journal of KIISE:Software and Applications
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• v.32 no.1
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• pp.10-21
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• 2005

Software architecture is increasingly being viewed as a key design in developing complex software systems, which largely affects the achievement of quality attributes. During the architecture-based software development, therefore, architectural transformation is needed to achieve quality attributes. Due to the variety of design alternatives and the poor predictability of the effects of the transformation, however, it is not easy to apply architectural transformation. Therefore, the method is needed to support architectural transformation through systematically analyzing the effects of applying various design alternatives to the architecture. This paper proposes an approach to support software architecture transformation. Based on architectural design decisions and the constraints on them included in the architecture, our approach defines a decision constraint graph representing the dependencies among architectural design decisions. Through using the decision constraint graph, architectural transformation can be systematically performed by understanding the effects of applying a transformation. While this work supports more understanding of applying architectural transformation, it also helps reconstruct a software architecture to improve the quality of the software.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1528-1531
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• 2013

본 논문은 스테레오 시각에서 3차원 정보를 얻기 위해 bilateral filter를 이용한 그래프 컷 기반의 다해상도 스테레오 영상 정합 방법을 제안하고자 한다. 제안한 방법은 변위도에서 물체의 경계를 명확히 구분하기 위해 bilateral filter를 이용하여 그래프의 각 노드들을 연결하는 경로의 가중치를 결정하고 정합 비용을 통합한다. 정합 과정에서 계산복잡도를 줄이기 위해 계층적 다해상도 구조를 적용하여 영상 피라미드를 만들고, 정합의 정확성을 향상시키기 위해 정합 영역에 변위 평활성과 같은 제약 조건을 적용하여 변위를 전파하는 방법을 사용한다. 실험을 통해 제안한 방법이 변위 탐색 시간을 감소시킬 뿐만 아니라 기존의 그래프 컷의 단점을 보완할 수 있음을 확인하고자 한다.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.11-18
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• 2005

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by $62.2\%$ than those of DDMAP. And reduced the number of CLBs by $17.6\%$ than those of TEMPLA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1132-1138
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• 2002

This paper proposes a reducing power consumption of a scheduling algorithm for optimal selection of supply voltage. In scheduling of reduction power consumption, we determine the control steps of operations to be executed by exploiting the possibility of using variable voltage levels to reduce power consumption. In the optimal selection of supply voltage binding, we minimize the main factor of the power consumption of the switching activity on the registers using a graph coloring technique. From a set of experiments using high-level benchmark examples, we show that the proposed algorithm prefer to use optimal selection supply voltages rather than uniformed single voltage is effective in reducing power consumption.

• Journal of KIISE:Software and Applications
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• v.33 no.1
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• pp.114-129
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• 2006

Ontology mapping is the task of finding semantic correspondences between two ontologies. In order to improve the effectiveness of ontology mapping, we need to consider the characteristics and constraints of data models used for implementing ontologies. Earlier research on ontology mapping, however, has proven to be inefficient because the approach should transform input ontologies into graphs and take into account all the nodes and edges of the graphs, which ended up requiring a great amount of processing time. In this paper, we propose a multi-strategic mapping approach to find correspondences between ontologies based on the syntactic or semantic characteristics and constraints of the topic maps. Our multi-strategic mapping approach includes a topic name-based mapping, a topic property-based mapping, a hierarchy-based mapping, and an association-based mapping approach. And it also uses a hybrid method in which a combined similarity is derived from the results of individual mapping approaches. In addition, we don't need to generate a cross-pair of all topics from the ontologies because unmatched pairs of topics can be removed by characteristics and constraints of the topic maps. For our experiments, we used oriental philosophy ontologies, western philosophy ontologies, Yahoo western philosophy dictionary, and Yahoo german literature dictionary as input ontologies. Our experiments show that the automatically generated mapping results conform to the outputs generated manually by domain experts, which is very promising for further work.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• Journal of Intelligence and Information Systems
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• v.13 no.3
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• pp.101-117
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• 2007

In this paper, we propose a customized genetic algorithm (GA) to find the minimum-cost guideway network (GN) of personal rapid transit (PRT) subject to connectivity, reliability, and traffic capacity constraints. PRT is a novel transportation concept, where a number of automated taxi-sized vehicles run on an elevated GN. One of the most important problems regarding PRT is how to design its GN topology for given station locations and the associated inter-station traffic demands. We model the GN as a directed graph, where its cost, connectivity, reliability, and node traffics are formulated. Based on this formulation, we develop the GA with special genetic operators well suited for the GN design problem. Such operators include steady state selection, repair algorithm, and directed mutation. We perform numerical experiments to determine the adequate GA parameters and compare its performance to other optimization algorithms previously reported. The experimental results verify the effectiveness and efficiency of the proposed approach for the GN design problem having up to 210 links.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.85-94
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• 2015

In this paper, an enhanced QoS multicast routing scheduling scheme is proposed to adapt to a dynamic mobile traffic condition for wireless mesh networks (WMNs). It handles the network QoS by controlling the delay constraints for multimedia applications. The group size will be controlled according to both the current network state and QoS requirements. The dynamic reconstruction of QoS multicast tree can be obtained from preprocessing with both the partial multicast routing scheme and the traffic estimation. Performance evaluation of the proposed scheme is carried out on randomly generated graph derived from the wireless mesh network, by choosing the optimal value related to the appropriate delay bounds. Simulation results show that the proposed scheme can improve the performance of QoS multicast routing for WMNs.