• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1815-1821
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• 2006

In this paper, the subthreshold swing has been analyzed for FinFET under channel length of 20nm. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current and WKB(Wentzel-Kramers-Brillouin) approximation to tunneling current. The cutoff current is obtained by simple adding two currents since two current is independent. The subthreshold swings by this model are compared with those by two dimensional simulation and two values agree well. Since the tunneling current increases especially under channel length of 10nm, the characteristics of subthreshold swing is degraded. The channel and gate oxide thickness have to be fabricated as am as possible to decrease this short channel effects, and this process has to be developed. The subthreshold swings as a function of channel doping concentrations are obtained. Note that subthreshold swings are resultly constant at low doping concentration.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.5
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• pp.70-78
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• 2001

We have developed a novel driving system of 5' true color FED using voltage controlled PWM method which has current control effect. The proposed method has the advantage of voltage controlled pulse width modulation method and current control method. Also, we propose a new circuit model of FED subpixel for circuit simulation of FED driving circuits, considering some parasitic effects, i.e., cross talk, line coupling effect and leakage current to the adjacent cathode lines. Output stage of the data driving circuit is optimized using the proposed circuit model. In video data processing, FED controller uses the parallel processing of R.G.B input data, so duty ratio is maximized and brightness of FED increases. With this results, no noise and high quality performance is achieved in display of 5' true color FED.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.144-152
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• 1996

In this paper, a pulse-mode digital multilayer neural network with a massively parallel yet compact and flexible network architecture is presented. Algebraicneural operations are replaced by stochastic processes using pseudo-random pulse sequences and simple logic gates are used as basic computing elements. The distributions of the results from the stochastic processes are approximated using the hypergeometric distribution. A statistical model of the noise(error) is developed to estimate the relative accuracy associated with stochastic computing in terms of mean and variance. Numerical character recognition problems are applied to the network to evaluate the network performance and to justify the validity of analytic results based on the developed statistical model. The network architectures are modeled in VHDL using the mixed descriptions of gate-level and register transfer level (RTL). Experiments show that the statistical model successfully predicts the accuracy of the operations performed in the network and that the character classification rate of the network is competitive to that of ordinary Back-Propagation networks.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.28 no.5B
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• pp.575-589
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• 2008

In the present work, we investigate the hydrodynamic behavior of a turbulent bore, such as tsunami bore and tidal bore, generated by the removal of a gate with water impounded on one side. The bore generation system is similar to that used in a general dam-break problem. In order to the numerical simulation of the formation and propagation of a bore, we consider the incompressible flows of two immiscible fluids, liquid and gas, governed by the Navier-Stokes equations. The interface tracking between two fluids is achieved by the volume-of-fluid (VOF) technique and the M-type cubic interpolated propagation (MCIP) scheme is used to solve the Navier-Stokes equations. The MCIP method is a low diffusive and stable scheme and is generally extended the original one-dimensional CIP to higher dimensions, using a fractional step technique. Further, large eddy simulation (LES) closure scheme, a cost-effective approach to turbulence simulation, is used to predict the evolution of quantities associated with turbulence. In order to verify the applicability of the developed numerical model to the bore simulation, laboratory experiments are performed in a wave tank. Comparisons are made between the numerical results by the present model and the experimental data and good agreement is achieved.

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.1-9
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• 2018

Low-power long-range networks (LoRa) has a comprehensive coverage of up to 30 km, so that long-range positioning is possible. However, the position error in the current LoRa environment is over 500 m. This makes it difficult to use practical location services in the LoRa environment. In this paper, we propose a method to improve the position accuracy by correcting an inaccurate visual error when sending a signal from a mobile node to a gateway through the reference node of each zone in the LoRa environment. Experiments were carried out using MATLAB, and a radio propagation algorithm, the Hata model, was used to cancel out the stationary noise and to evaluate the environmental noise. Experimental results showed that the error range decreased as the number of reference nodes increased and a mobile node approach the reference node.

• Journal of KIISE:Information Networking
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• v.36 no.1
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• pp.1-11
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• 2009

In this paper, we propose a QoS routing protocol for WiMAX based wireless mesh networks. The proposed routing protocol is a proactive hop-by-hop QoS routing protocol. It can find an optimal route that satisfies QoS requirements using bandwidth and delay as QoS parameters. In this paper, we first present a network model for WIMAX based wireless mesh networks and explain why QoS routing protocol is the most appropriate for WiMAX based wireless mesh networks. Then, we propose a proactive hop-by-hop QoS routing protocol that meets QoS requirements of traffic flowing between mesh client and the gateway. The simulation results show that the proposed routing protocol outperforms QOLSR protocol in terms of end-to-end delay, packet delivery ratio and routing overhead.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2509-2515
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• 2014

In this paper, the conventional vertical structure for VLSI circuits CMOS intend to improve the stress effects of active region and built-in threshold voltage. For these improvement, the proposed structure is shallow trench isolation of moat shape. We want to analysis the electron concentration distribution, gate bias vs energy band, thermal stress and dielectric enhanced field of thermal damage between vertical structure and proposed moat shape. Physically based models are the ambient and stress bias conditions of TCAD tool. As an analysis results, shallow trench structure were intended to be electric functions of passive as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.