• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.153-164
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• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.48-61
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• 1989

In this paper, two-dimensional numerical simulation of GaAs MESFFT with 0.7${\mu}m$ gate length is perfomed. Drift-diffusion model which consider that mobility is a function of local electric field, is used. As a discretization method, instead of FDM (finite difference method) and FEM (finite element method), the Control-Volume Formulation (CVF) is used and as a numerical scheme current hybrid scheme or upwind scheme is replaced by power-law scheme which is very approximate to exponential scheme. In the process of numerical analysis, Peclet number which represents the velocity ratio of drift and diffusion, is introduced. And using this concept a current equation which consider numerical scheme at the interface of control volume, is proposed. The I-V characteristics using the model and numerical method has a good agreement with that of previous paper by others. Therefore, it is confined that it may be useful as a simulator for GaAs MESFET. Besides I-V characteristics, the mechanism of both velocity saturation in drift-diffusion model is described from the view of velocity and electric field distribution at the bottom of the channel. In addition, the relationship between the mechanism and position of dipole and drain current, are described.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.69-76
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• 2016

Current driving capability of MCT (MOS Controlled Thyristor) is determined by turn-off capability of conducting current, that is off-FET performance of MCT. On the other hand, having a good turn-on characteristics, including high peak anode current ($I_{peak}$) and rate of change of current (di/dt), is essential for pulsed power system which is one of major application field of MCTs. To satisfy above two requirements, careful control of on/off-FET performance is required. However, triple diffusion and several oxidation processes change surface doping profile and make it hard to control threshold voltage ($V_{th}$) of on/off-FET. In this paper, we have demonstrated the effect of $V_{th}$ adjustment ion implantation on the performance of MCT. The fabricated MCTs (active area = $0.465mm^2$) show forward voltage drop ($V_F$) of 1.25 V at $100A/cm^2$ and Ipeak of 290 A and di/dt of $5.8kA/{\mu}s$ at $V_A=800V$. While these characteristics are unaltered by $V_{th}$ adjustment ion implantation, the turn-off gate voltage is reduced from -3.5 V to -1.6 V for conducting current of $100A/cm^2$ when the $V_{th}$ adjustment ion implantation is carried out. This demonstrates that the current driving capability is enhanced without degradation of forward conduction and turn-on switching characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.1
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• pp.15-22
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• 2008

In this paper, we propose a numerical analysis on reversed current of distributed amplifier based on transmission line theory and proposed a theory to obtain optimum transmission line length to minimize the reversed currents by cancelling those components. The reversed current is analyzed as being simply absorbed into the terminal resistance in the conventional analysis. In the proposed analysis, however, they are designed to be cancelled by each other with opposite phase by the optimal length of the transmission lint Circuit simulation and implementation using pHEMT transistor were performed to validate the proposed theory with the cutoff frequency of 3.6 GHz. From the measurement, maximum gain of 14.5dB and minimum gain of 12.3dB were achieved In the operation band. Moreover, measured efficiency of the proposed distributed amplifier is 25.6% at 3 GHz, which is 7.6%, higher than the conventional distributed amplifier. Measured output power Is about 10.9dBm, achieving 1.7dB higher output power than the conventional one. Those improvement is thought to be based on the cancellation of refersed current.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.46-54
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• 2018

The Internet of Things (IoT) is an environment in which various devices provide services to users through communications. Because of the nature of the IoT, data are stored and distributed in heterogeneous information systems. In this situation, IoT end applications should be able to access data without having information on where the data are or what the type of storage is. This mechanism is called Service Discovery (SD). However, some problems arise, since the current SD architectures search for data in physical devices. First, turnaround time increases from searching for services based on physical location. Second, there is a need for a data structure to manage devices and services separately. These increase the administrator's service configuration complexity. As a result, the device-oriented SD structure is not suitable to the IoT. Therefore, we propose an SD structure called Name-based Service-centric Service Discovery (NSSD). NSSD provides name-based centralized SD and uses the IoT edge gateway as a cache server to speed up service discovery. Simulation results show that NSSD provides about twice the improvement in average turnaround time, compared to existing domain name system and distributed hash table SD architectures.