• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.144-152
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• 1996

In this paper, a pulse-mode digital multilayer neural network with a massively parallel yet compact and flexible network architecture is presented. Algebraicneural operations are replaced by stochastic processes using pseudo-random pulse sequences and simple logic gates are used as basic computing elements. The distributions of the results from the stochastic processes are approximated using the hypergeometric distribution. A statistical model of the noise(error) is developed to estimate the relative accuracy associated with stochastic computing in terms of mean and variance. Numerical character recognition problems are applied to the network to evaluate the network performance and to justify the validity of analytic results based on the developed statistical model. The network architectures are modeled in VHDL using the mixed descriptions of gate-level and register transfer level (RTL). Experiments show that the statistical model successfully predicts the accuracy of the operations performed in the network and that the character classification rate of the network is competitive to that of ordinary Back-Propagation networks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of IKEEE
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• v.14 no.1
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• pp.55-64
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• 2010

In this paper, we proposed the novel TIGBT with an additional p-type MOS structure to achieve the improved trade-off between turn-off and on-state voltage drop(Vce(sat)). These low on-resistance and the fast switching characteristics of the proposed TIGBT are caused by an enhanced electron current injection efficiency which is caused by additional p-type MOS structure. In the simulation result, the proposed TIGBT has the lower on state voltage of 1.67V and the shorter turn-off time of 3.1us than those of the conventional TIGBT(2.25V, 3.4us).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.10
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• pp.859-876
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• 2012

Since the existing protocols separated mobility management part and routing protocol part in their design and used a flooding, they suffer from the high control overhead, thereby limiting performance. In this paper, we use a tree-based mobility management method and present a simple and efficient routing protocol that exploits the topology information which is built additionally through mobility management. Thus, the mobility management and the routing protocol closely cooperate to optimize control overhead. Furthermore, we use a progressive path discovery method to alleviate traffic congestion around IG and a unicast-based broadcast method to increase the reliability of message delivery and to judge link validity promptly. The proposed protocol reduces control overhead greatly and works in a stable manner even with the large number of nodes and high mobility. This was proven by comparing with the AODV protocol that employs the hybrid mobility management protocol.

• Journal of Internet Computing and Services
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• v.9 no.4
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• pp.21-27
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• 2008

TCP receivers deliver ACK packets to senders for reliable end-to-end transfer. When ACK packets are not transferred properly because of network congestion, the performance of TCP degrades. This paper proposes a reverse congestion warning mechanism and a congestion handling mechanism in heterogeneous networks with heavy background traffic in the backward direction. Help from TCP receivers or hardware such as routers and gateways other than the ACK packets themselves is not necessary. TCP senders compare the arrival intervals of ACK data passed from receivers and the difference in t imestamp values echoed by receivers. According to the simulation results using the NS-2 network simulator, the proposed scheme shows a performance elevation of 20% greater than Reno, 150% greater than New Reno, and 450% greater than Westwood, respectively, under heterogeneous networks and that the error rate of the radio link is 1% when the backward network is congested.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.33-41
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• 2014

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1369-1376
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• 2015

A wireless bridge is essential to transmit control and managing information to sensors or instruments from a central integrated ship area network station. In this paper, a WiMedia Distributed-MAC(D-MAC) protocol is adopted for development of a seamless N-Screen wireless service in Indoor and Ship Area Networks. Furthermore, to provide the OSMU(One Source Multi Use) N-screen service through P2P streaming in the seamless D-MAC protocol, a Dynamic Threshold-based Multicast(DTM) technology is proposed and analyzed. For this technology, a new Hard/Soft Vertical Region(HVR-SVR) based time slot allocation and a multicast resource reservation scheme are combined. From simulation results, proposed DTM scheme expands the number of time slots available for unicast and multicast realtime N-Screen reservations with various service time interval requests. Furthermore, it enhances performances in vewpoints of realtime N-Screen data reservation conflict and throughput.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3B
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• pp.398-407
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• 2010

Due to increase of user requirement for various traffics and the advance of network technology, each distinct network has converge into FMC(Fixed Mobile Convergence) networks. However, we need to research the performance analysis of VoIP(Voice over Internet Protocol) in the FMC network to provide QoE for the voice user of FMC network. Therefore, this paper introduces the scenario which is the situation of voice quality degradation when a user uses VoIP to communicate with other users in the FMC network. Especially, this paper presents scenario in terms of the component of the network and finds the improvement point of voice quality. In the simulation results, three improvement points of voice quality are found as following: voice quality degradation by packet loss in the physical layer of the HSDPA network, by utilizing GGSN without QoS parameter mapping mechanism which is gateway between 3GPP and IP backbone, and by using non-QoS AP in the WLAN network.