• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.351-355
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• 2006

RSA 암호 시스템은 IC카드, 모바일 및 WPKI, 전자화폐, SET, SSL 시스템 등에 많이 사용된다. RSA는 모듈러 지수승 연산을 통하여 수행되며, Montgomery 곱셈기를 사용하는 것이 효율적이라고 알려져 있다. Montgomery 곱셈기에서 임계 경로 지연 시간(Critical Path Delay)은 세 피연산자의 덧셈에 의존하고 캐리 전파를 효율적으로 처리하는 문제는 Montgomery 곱셈기의 효율성에 큰 영향을 미친다. 최근 캐리 전파를 제거하는 방법으로 캐리 저장 덧셈기(Carry Save Adder, CSA)를 사용하는 연구가 계속 되고 있다. McIvor외 세 명은 지수승 연산에 최적인 CSA 3단계로 구성된 Montgomery 곱셈기와 CSA 2단계로 구성된 Montgomery 곱셈기를 제안했다. 시간 복잡도 측면에서 후자는 전자에 비해 효율적이다. 본 논문에서는 후자보다 빠른 연산을 수행하기 위해 캐리 전파 제거 특성을 가진 이진 부호 자리(Signed-Digit, SD) 수 체계를 사용한다. 두 이진 SD 수의 덧셈을 수행하는 잉여 이진 덧셈기(Redundant Binary Adder, RBA)를 새로 제안하고 Montgomery 곱셈기에 적용한다. 기존의 RBA에서 사용하는 이진 SD 덧셈 규칙 대신 새로운 덧셈 규칙을 제안하고 삼성 STD130 $0.18{\mu}m$ 1.8V 표준 셀 라이브러리에서 지원하는 게이트들을 사용하여 설계하고 시뮬레이션 하였다. 그 결과 McIvor의 2 방법과 기존의 RBA보다 최소 12.46%의 속도 향상을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1815-1821
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• 2006

In this paper, the subthreshold swing has been analyzed for FinFET under channel length of 20nm. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current and WKB(Wentzel-Kramers-Brillouin) approximation to tunneling current. The cutoff current is obtained by simple adding two currents since two current is independent. The subthreshold swings by this model are compared with those by two dimensional simulation and two values agree well. Since the tunneling current increases especially under channel length of 10nm, the characteristics of subthreshold swing is degraded. The channel and gate oxide thickness have to be fabricated as am as possible to decrease this short channel effects, and this process has to be developed. The subthreshold swings as a function of channel doping concentrations are obtained. Note that subthreshold swings are resultly constant at low doping concentration.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.597-607
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• 2014

An integrated ship area network has functionality of remote control and autonomous management of various sensors and instruments embedded or boarded in a ship. For such environment, a wireless bridge is essential to transmit control and/or managing information to sensors or instruments from a central integrated ship area network station. In this paper, one of reliable schemes of wireless bridge using WiMedia distributed MAC (D-MAC) protocol is proposed to increase a communication reliability. Simulation results show that the proposed wireless bridge using WiMedia D-MAC protocol guarantees reliable communications between 2-hop devices.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.34-45
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• 2013

Due to its self-configuring nature, the tactical mobile ad hoc network is used for communications between tactical units and the command and control center (CCC) in battlefields, where communication infrastructure is not available. However, when a tactical unit moves far away from the CCC or there are geographical constraints, the data link between two communicating nodes can be broken, which results in an invalid data route from the tactical units to CCC. In order to address this problem, in this paper we propose a hierarchical connectivity maintenance scheme, namely ADLCoM (Autonomous Data Link Connectivity Maintenance). In ADLCoM, each tactical unit has one or more GW (gateway), which checks the status of data links between tactical units. If there is a possibility of link breakage, GWs request ground or aerial unmanned vehicles to become a relay for the data link. The simulation results, based on tactical scenarios, show that the proposed scheme can significantly improve the network performance with respect to data delivery ratio.

• The KIPS Transactions:PartC
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• v.15C no.6
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• pp.539-546
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• 2008

In this paper, we propose an address autoconfiguration mechanism and a route establishment mechanism appropriate for the modified MANET architecture which overcomes the multi-link subnet problem. For the delivery of Router Advertisement (RA) messages without causing the duplicate packet reception problem in the multi-hop wireless network environment, the Scope-Extended RA (Scope-Extended Router Advertisement) message is defined. Also, by defining the MANET Prefix option, a MANET node is allowed to send packets destined to a host not in the MANET directly to the gateway. This can prevent the performance degradation caused by broadcasting control messages of the reactive routing protocol for route establishment. The performance of the proposed mechanism is analyzed through NS-2 based simulations and, according to the simulation results, it is shown that the proposed mechanism performs well in terms of the control message overhead.

• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.6
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• pp.1185-1192
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• 2015

A wireless bridge is essential to transmit control and managing information to sensors or instruments from a central integrated ship area network station. In this paper, a WPAN protocol is adopted for development of a seamless N-screen wireless service in Indoor and Ship Area Networks. Furthermore, to provide the OSMU (One Source Multi Use) N-screen service through P2P streaming in the seamless WPAN protocol, a Grid-based WPAN networking technology is proposed and analyzed. The proposed Grid-based WPAN networking technology supports multi-path and fast path-setup functions for N-screen communications. The simulation results demonstrate that the proposed Grid-based WPAN networking technology outperforms the IEEE 802.15.4 based network in terms of N-screen transmission delay.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.5
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• pp.70-78
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• 2001

We have developed a novel driving system of 5' true color FED using voltage controlled PWM method which has current control effect. The proposed method has the advantage of voltage controlled pulse width modulation method and current control method. Also, we propose a new circuit model of FED subpixel for circuit simulation of FED driving circuits, considering some parasitic effects, i.e., cross talk, line coupling effect and leakage current to the adjacent cathode lines. Output stage of the data driving circuit is optimized using the proposed circuit model. In video data processing, FED controller uses the parallel processing of R.G.B input data, so duty ratio is maximized and brightness of FED increases. With this results, no noise and high quality performance is achieved in display of 5' true color FED.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.54-62
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• 2004

In this paper, we discuss on the design of a current mode CMOS multiplier circuit over $GF(3^m)$. Using the standard basis, we show the variation of vector representation of multiplicand by multiplying primitive element α, which completes the multiplicative process. For the $GF(3^m)$ multiplicative circuit design, we design GF(3) adder and multiplier circuit using current mode CMOS technology and get the simulation results. Using the basic gates - GF(3) adder and multiplier, we build the $GF(3^m)$ multiplier circuit and show the examples for the case m=3. We also propose the assembly of the operation blocks for a complete $GF(3^m)$ multiplier. Therefore, the proposed circuit is easily extensible to other p and m values over $GF(p^m)$ and has advantages for VLSI implementation. We verify the validity of the proposed circuit by functional simulations and the results are provided.