• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1445-1456
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• 2011

This paper presents the research of Low Pass Filter(hereinafter called "LPF") which is the part of Chopper Gate Control Unit on the electric rolling stock. Chopper Gate Control Unit controling the propulsive equipments of electric rolling stock consists of several electronic parts, PCB, Power Supply, Gate Circuit Amp, Freon Cooling Device, and has been used the parts made by japan manufacturer Mitsubish. But these parts recently have been more broken down and slow down performance because of long-term use, deterioration. Most of the malfunctions are low performance of LPF. Furthermore, it is physically impossible to repair LPF. Because it is molding type part and no longer manufactured. Also it needs high cost for custom-building. Therefore, it is now making up for through self-developed LPF and operating on Busan metro 1st after on-board testing. This research performed the PS Pice simulation testing, analysis of self-developed LPF performance and the wave form characteristic by multi-function synthesizer, spectrum analyzer, oscilloscope.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.1
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• pp.81-86
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• 2016

The valves used to control or shut off the flow through a pipeline can be divided into many different types, including gate valves, globe valves, and check valves. Globe valves, in particular, have excellent properties, and because they can easily control the flow under high-pressure conditions, they are generally used in LNG ship and steam pipelines. In this paper, a method for changing the shape of a seat was suggested to solve the valve leakage problem from a structural perspective. In addition, the stress distribution and directional deformation were compared for each model. The suggested models were thus validated, and the optimized seat structure, which includes a self-supporting capability for decreasing the amount of leakage, was determined.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.143-152
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• 2012

In this paper hardware implementation of GF($2^{191}$) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF($2^m$), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of IKEEE
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• v.12 no.4
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• pp.255-262
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• 2008

In this paper, we proposed the novel IGBT with an additional n-type MOS structure to achieve the improved trade-off between turn-off and on-state voltage drop(Vce(sat)). These low on-resistance and the fast switching characteristics of the proposed IGBT are caused by an enhanced electron current injection efficiency which is caused by additional n-type MOS structure. In the simulation result, the proposed IGBT has the lower on state voltage of 2.65V and the shorter turn-off time of 4.5us than those of the conventional IGBT(3.33V, 5us).

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.1-9
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• 2018

Low-power long-range networks (LoRa) has a comprehensive coverage of up to 30 km, so that long-range positioning is possible. However, the position error in the current LoRa environment is over 500 m. This makes it difficult to use practical location services in the LoRa environment. In this paper, we propose a method to improve the position accuracy by correcting an inaccurate visual error when sending a signal from a mobile node to a gateway through the reference node of each zone in the LoRa environment. Experiments were carried out using MATLAB, and a radio propagation algorithm, the Hata model, was used to cancel out the stationary noise and to evaluate the environmental noise. Experimental results showed that the error range decreased as the number of reference nodes increased and a mobile node approach the reference node.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.173-179
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• 2002

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.851-858
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• 2017

In this study, the voltage control system of a single phase full bridge inverter was designed based on the SPWM driving method. The voltage control system consists of a single-phase full-bridge inverter, a PI controller for linearly compensating the error between the reference voltage and the output voltage, a PWM driving circuit for generating the gate signal using the SPWM method from the controller signal, and an LC filter for filtering the inverter output voltage waveform into sinusoidal waveform. Finally, the voltage control system of a single-phase full-bridge inverter based on the PWM driving method was modeled using EMTP-RV and by showing that the output voltage accurately converges the reference voltage through several simulation examples, the validity of the control system design was verified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1349-1359
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• 1998

In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

• Journal of KIISE:Information Networking
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• v.36 no.1
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• pp.1-11
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• 2009

In this paper, we propose a QoS routing protocol for WiMAX based wireless mesh networks. The proposed routing protocol is a proactive hop-by-hop QoS routing protocol. It can find an optimal route that satisfies QoS requirements using bandwidth and delay as QoS parameters. In this paper, we first present a network model for WIMAX based wireless mesh networks and explain why QoS routing protocol is the most appropriate for WiMAX based wireless mesh networks. Then, we propose a proactive hop-by-hop QoS routing protocol that meets QoS requirements of traffic flowing between mesh client and the gateway. The simulation results show that the proposed routing protocol outperforms QOLSR protocol in terms of end-to-end delay, packet delivery ratio and routing overhead.