• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1170-1175
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• 2003

In this paper, the output power improvement of Push-Push FET DRO by adding the identical DR at the drain port as one used in the gate port, has been theoretically investigated. The investigation shows that the DR located between two microstrip lines locks the phase difference of two FET's outputs at 180 degree and improves the output power of Push-Push FET DRO. Since this effect can be used for correcting the impedance difference between two FETs output circuits and the electrical length error of the power combiner at the output circuit of Push-Push DRO, which may occur when fabricate the oscillator, the oscillator with an additional DR can be useful structure for fabricating oscillator.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.5
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• pp.521-526
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• 1999

It was investigated that traps were generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The charge state of the traps can easily be changed by application of low voltage after the stress high voltage. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$to 814$\AA$ with capacitor areas of $10^{-3}{$\mid$textrm}{cm}^2$. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.8B
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• pp.1122-1128
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• 2010

In this paper, we proposed and designed a novel SNA protocol which operates in the way of a server and a client in the power control system. The proposed SNA protocol includes the information about the mode switching, the saving position of context information, the user trigger, and so forth, which are needed in the power management devices. We consider the application of the SNA protocol to the home network, where message flows between the SNA server and the SNA client. To verify the operation of the SNA protocol, the state transition diagrams of the server in the home gateway and the client in the network device are shown. Hence, we can conclude the SNA can operate without malfuction.

• Information and Communications Magazine
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• v.32 no.7
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• pp.63-71
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• 2015

클라우드 컴퓨팅이란 공유된 IT 자원을 네트워크 상에서 가상화를 통하여 독립적으로 사용할 수 있는 개념으로 저탄소 녹색시대를 위한 에너지 절감 솔루션이다. 특히 비용 절감이 필수적인 기업과 공공기관 등에서 IT 자원의 개별적 소유에 시간과 비용을 투입하지 않고 사용한만큼의 비용을 지불할 수 있다. 이에 정부에서는 2015년 9월부터 시행되는 클라우드법 제정을 통하여 클라우드 컴퓨팅의 활성화를 적극 장려하고 있다. 그러나 신뢰성있는 서비스 제공을 위해서는 보안성, 성능, 안정성 제공을 위한 네트워크 기능의 한계 극복이 필수적이다. 이에 본 논문에서는 언제 어디서나 다양한 기기로 업무를 수행할 수 있는 모바일 스마트워크가 가능하도록 하는 단말과 기업망, 클라우드를 안전하게 연결하는 가상 사설 클라우드(Virtual Private Cloud) 네트워킹 구조를 제안한다. 본 구조에서는 클라우드 내에서 사설 주소의 중복 문제 해결을 위하여 위치 주소와 아이디 분리 프로토콜 기반 위에 기업망 등의 엔터프라이즈 ID 개념을 적용하여 주소 확장성을 제공하였다. 또한 이러한 기술을 적용한 VPC 매니저, 서비스 게이트웨이 및 에이전트로 구성된 VPC 네트워킹 솔루션으로 테스트베드를 구축하고 그 운용 경험을 통해서 실 사업자망에 적용 가능한 비즈니스 모델 도출이 가능할 것으로 기대한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2171-2179
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• 2009

In this paper, we propose a novel Image Encryption using MLCA (Maximum Length Cellular Automata) and CAT (Cellular Automata Transform). Firstly, we use the Wolfram rule matrix to generate MLCA state transition matrix T. Then the state transition matrix T changes pixel value of original image according to pixel position. Next, we obtain Gateway Values to generate 2D CAT basis function. Lastly, the basis function encrypts the MLCA encrypted image into cellular automata space. The experimental results and security analysis show that the proposed method guarantees better security and non-lossy encryption.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.173-174
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• 2014

본 논문에서는 저 대기전력 구현이 가능하며 정확한 출력전압 제어가 가능한 SSR(Secondary Side Regulator) 플라이백 컨버터를 제안하였다. 제안 SSR 플라이백 컨버터는 2차 측에 control IC를 사용하여 별도의 제어기(TL431) 및 포토커플러를 제거하여 구조가 간단하고 대기모드 시 TL431의 바이어스 전류에 의한 전력소모를 줄일 수 있으므로 대기전력을 최소화 할 수 있으며 출력전압을 직접 검출하여 정확하게 출력을 제어할 수 있다. 한편 1차 측의 위치한 게이트 구동을 위해 절연된 1-2차 측간 신호를 전송하는 PET(Pulse Edge Transmitter)를 제안하였으며 제안 방식은 IC로의 직접화가 매우 용이하여 1-2차 측 IC와 제안 PET를 one-chip화 할 수 있다. 제안 회로의 타당성 검증을 위해 10W급 Adaptor의 시작품을 제작하였고, 이를 이용한 실험결과를 바탕으로 제안 시스템의 타당성을 검증한다.

• The Journal of Information Technology
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• v.3 no.3
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• pp.57-65
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• 2000

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.540-548
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• 2007

The parer proposes a power factor correction high efficiency PWM single-phase rectifier. Its good characteristics such as simple PWM control, low switch stress, and low VAR rating of commutation circuits make the proposed rectifier very suitable for various unidirectional power applications. In addition, the proposed rectifier consists of three boost-converter-type IGBT modules with the switching devices located at the bottom leg of the rectifier scheme, which also enables the use of the same power supply in both control and gate driver, thus resulting in simple control and power circuit structure. The detailed principle of operation and experimental results are also included. In particular, the design guide line is also suggested to make the circuit design of the proposed rectifier easy and fast.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.343-346
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• 2009

Since an LFSR as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for a pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers have studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG.

• Journal of IKEEE
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• v.27 no.4
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• pp.630-635
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• 2023

SiC is replacing the position of silicon in the power semiconductor field due to its superior resistance to adverse conditions such as high temperature and high voltage compared to silicon, which occupies the majority of existing industrial fields. In this paper, the gate of 4H-SiC Planar MOSFET, one of the power semiconductor devices, was formed with aluminium to make the contrast and parameter values consistent with polycrystalline Si gate, and the threshold voltage, breakdown voltage, and IV characteristics were studied by varying the channel doping concentration of SiC MOSFET.