• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.5 no.2
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• pp.10-19
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• 1994

The error rate equation of Reed-Solomon/Convoutional concatenated coded MFSK signal transmitted over m-distributed fading channel with Additive White Gaussian Noise (AWGN) and re- ceived with Maximal Ratio Combining (MRC) diversity has been derived. The bit error probability has been evaluated using the derived equation and shown n figures as a function of signal to noise ratio, fading index and the number of diversity branches. From the results obtained, we have shown that the bit error probability of MFSK signal is improved by using coding technique in fading environment. The concatenated coding technique is found to be very effective. When concatenated coding and MRC diversity reception techniques are used together in fading environ- ment, the improvement of error performance attains about 6.6 dB in terms of SNR as compared with that of employing only concatenated coding case.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.4
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• pp.611-617
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• 1998

In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and wire secure communications are investigated. A secure communication method in which the desired information signal is synthesized with the chaos signal created by the Chua's circuit is proposed and an information signal is demodulated also using the Chua's circuit. The proposed method is synthesizing the desired information with the chaos circuit by adding the information signal to the chaos signal in the wire transmission system. After transmitting the synthesized signal through the wire transmission system, it is confirmed the feasibility of the secure communication from the result of the demodulated signals and the recovered wire tapped signals.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.967-971
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• 2009

The histogram equalization algorithm is the most crucial algorithm for image enhancement. Since its direct hardware implementation always requires a divider or multiplier, its implementation cost tends to increas as the image resolution is increased or diverse image resolutions are handled. In this paper, we propose a divider-free reconstruction of histogram equalization algorithm and the corresponding hardware architecture. The logic synthesis results show that the proposed scheme can reduce the logic gate count by 84.2% compared to the conventional implementation example when the UXGA resolution is considered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1539-1545
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• 1999

In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and a wire secure communications are investigated. A secure communication method in which the desired information signal is synthesized with the chaos signal created by the Chua's circuit is proposed and information signal is demodulated also using the Chua's circuit. The proposed method is synthesizing the desired information with the chaos circuit by adding the information signal to the chaos signal in the wire transmission system. After transmitting the synthesized signal through the wire transmission system, it is confirmed the feasibility of the secure communication from result of demodulated signals recovered wire tapped signals.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.241-250
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• 2000

Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor, and a nonlinear resistor. In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and synchronizations and secure communication of a lossy equivalent transmission are investigated. Since the synchronization of the lossy equivalent transmission system is impossible by coupled synchronization, theory having both the drive-response and the coupled synchronization is proposed. The proposed method is synthesizing the desired information with the chaos circuit by adding the information signal to the chaos signal in the lossy equivalent transmission system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.547-554
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• 2008

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.37-44
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• 2001

In this paper, an efficient architecture for the ECC multiplier in GF(2") is proposed. We give a design example for the irreducible trinomials $x_{193}\;+\;x_{15}\;+\;1$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. A digit-serial multiplier with a digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The elliptic curve used in this implementation is defined by Weierstrass equations. The measured results show that the proposed multiplier it 0.3 times smaller than the bit-serial LFSR multiplier.lier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.5
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• pp.2393-2399
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• 2013

In this paper, we proposed a method to screening of Alzheimer's disease (AD) from Raman spectra of platelet with synthesis of basis spectra using singular value decomposition (SVD). Raman spectra of platelet from AD transgenic mice are preprocessed with denoising, removal background and normalization method. The column vectors of each data matrix consist of Raman spectrum of AD and normal (NR). The matrix is factorized using SVD algorithm and then the basis spectra of AD and NR are determined by 12 column vectors of each matrix. The classification process is completed by select the class that minimized the root-mean-square error between the validation spectrum and the linear synthesized spectrum of the basis spectra. According to the experiments involving 278 Raman spectra, the proposed method gave about 97.6% classification rate, which is better performance about 6.1% than multi-layer perceptron (MLP) with extracted features using principle components analysis (PCA). The results show that the basis spectra using SVD is well suited for the diagnosis of AD by Raman spectra from platelet.