• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.327.1-327.1
• /
• 2014

Nitrides-on-silicon structures are considered to be an excellent candidate for unique design architectures and creating devices for high-power applications. Therefore, a lot of effort has been concentrating on growing high-quality III-nitrides on Si substrates, mostly Si(111) and Si(001) substrates. However, there are several fundamental problems in the growth of nitride compound semiconductors on silicon. First, the large difference in lattice constants and thermal expansion coefficients will lead to misfit dislocation and stress in the epitaxial films. Second, the growth of polar compounds on a non-polar substrate can lead to antiphase domains or other defective structures. Even though the lattice mismatches are reached to 16.9 % to GaN and 19 % to AlN and a number of dislocations are originated, Si(111) has been selected as the substrate for the epitaxial growth of nitrides because it is always favored due to its three-fold symmetry at the surface, which gives a good rotational matching for the six-fold symmetry of the wurtzite structure of nitrides. Also, Si(001) has been used for the growth of nitrides due to a possible integration of nitride devices with silicon technology despite a four-fold symmetry and a surface reconstruction. Moreover, Si(110), one of surface orientations used in the silicon technology, begins to attract attention as a substrate for the epitaxial growth of nitrides due to an interesting interface structure. In this system, the close lattice match along the [-1100]AlN/[001]Si direction promotes the faster growth along a particular crystal orientation. However, there are insufficient until now on the studies for the growth of nitride compound semiconductors on Si(110) substrate from a microstructural point of view. In this work, the microstructural properties of nitride thin layers grown on Si(110) have been characterized using various TEM techniques. The main purpose of this study was to understand the atomic structure and the strain behavior of III-nitrides grown on Si(110) substrate by molecular beam epitaxy (MBE). Insight gained at the microscopic level regarding how thin layer grows at the interface is essential for the growth of high quality thin films for various applications.

• Proceedings of the Korean Vacuum Society Conference
• /
• 1994.02a
• /
• pp.7-8
• /
• 1994

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.110-110
• /
• 2010

본 실험에서는 Silicon (001) 기판을 사용하여 silicon 기판상에 modified Stranski-Krastanow(S-K) 방식으로 InAs quantum dot (QD) 을 성장하고 그 위에 InSb layer를 형성하였다. 기판온도 $390^{\circ}$에서 In injection period를 4번 반복하여 제작된 InAs quantum dot layer를 buffer로 사용하였으며, QD layer의 밀도는 $1{\mu}m^2$ 당 600개, height가 $6.2\;{\pm}\;2.0\;nm$, width가 $36.1\;{\pm}\;9.2\;nm$ 정도이다. 성장된 $2.8{\mu}m$ 두께의 InSb film의 특성을 분석해 보면 AFM 상에서의 root mean square (rms) roughness는 5.142nm정도이며, electron mobility는 340 K 에서 $41,352cm^2/Vs$, 1.8 K에서는 $4,215cm^2/Vs$ 정도를 나타내었다. 본 실험에서는 다른 실험과는 달리 InAs QD 을 buffer layer로 사용하였으며, silicon기판도 아무런 처리가 되지 않은 (001)기판을 사용하였으므로 기존의 다른 연구 결과와는 차별성을 가진다. 또한 buffer로 사용된 InAs quantum dot layer의 종류를 한 가지로 고정하고 실험을 하였지만 추후 더욱 다양한 밀도와 크기의 quantum dot layer를 적용시키고, 기존의 다른 논문에서 적용된 방법들을 추가로 적용시켜 본다면 mobility값은 더욱 증가할 것으로 생각된다. 이러한 연구를 통해 값이 싸고 구하기 쉬운 silicon기판상에 silicon에 비하여 더 좋은 특성을 갖는 III-V족 화합물 반도체 소자를 구현 할 수 있을 것으로 생각된다.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.8
• /
• pp.950-958
• /
• 1988

We have implemented a RTA system using W-halogen lamps and tried to recrystallize the phosphorus ion implanted amorphous silicon on insultor (SOI) taking advantages of seeding window. The purpose of this study is to investigate the possibility of a typical crystalline orientation occurred during the solidifying process of molten amorphous silicon layer. Experimental results show that several twin boundaries are found on the seeding window region after annealing for 15 sec at 1040\ulcorner. These twin boundaries represent that the recrystallization is partialy possible and when the annealing is done at 1150\ulcorner, (100) etch pits with <110> facets are found on the solidified amorphous silicon layer. Consequently, Hall mobility of recrystallized silicon film is measured and the thermal behavior of grain boundary is also observed by SEM.

• Journal of the Korean Vacuum Society
• /
• v.4 no.S2
• /
• pp.64-68
• /
• 1995

Silicon films were deposited at $430^{\circ}C$ by remote plasma chemical vapor deposition(RPECVD) with a gas mixture of $Si_2H_6/SiF_4/H_2$. The silicon films deposited without and with $SiF_4$ were characterized using atomic force microscopy(AFM), transmission electron microscopy(TEM) and X-ray diffraction(XRD). Both silicon films have the same rugged surface morphology, but, the silicon film deposited with $SiF_4$ exhibits more rugged. The silicon film deposited without $SiF_4$ is amorphous, whereas the silicon film deposited with $SiF_4$ is polycrystalline with very small needle-like grains which are perpendicular to the substrate and uniformly distributed in the thickness of the film. The silicon film deposited with $SiF_4$ was found to have a preferred orientation along the growth direction with the<110> of the film parallel to the <111> of the substrate. The effect of $SiF_4$ during RPECVD was discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.92-92
• /
• 2009

본 논문에서는 strained Silicon-on-Insulator (sSOI) 기판에 제작된 triple-gate MOSFETs 의 이동도와 단채널 효과에 대하여 분석 하였다. Strained 실리콘에 제작된 소자는 전류의 방향이 <110> 밤항일 경우 전자의 이동도는 증가하나 정공의 이동도는 오히려 감소하는 문제점이 있다. 이를 극복하기 위하여 소자에서 전류의 방향이 <110>방향에서 45 도 회전된 <100> 방향으로 흐르게 제작하였다. Strain이 가해지지 않은 기판에 제작된 동일한 구조의 소자와 비교하여 sSOI 에 제작된 소자에서 전자의 이동도는 약 40% 정공의 이동도는 약 50% 증가하였다. 채널 길이가 100 nm 내외로 감소함에 따라 나타나는 drain induced barrier lowering (DIBL) 현상, subthreshold slope (SS)의 증가 현상에서 sSOI에 제작된 소자가 상대적으로 우수한 특성을 보였으며 off-current leakage ($I_{off}$) 특성도 sSOI기판이 더 우수한 특성을 보였다.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1509_1510
• /
• 2009

This paper presents the design and simulation results of ohmic contact RF MEMS silicon switch with a high isolation at high frequencies along with the position of a contact part, initial off-state and intermediate off-state including the state where a contact part is placed right over a signal line of coplanar waveguide (CPW). The ohmic contact part is connected with comb drives made of high resistivity single crystalline silicon. The released contact part is $30{\mu}m$ apart from the edge of signal line on the glass substrate along the lateral direction (x-direction) at initial off-state. The electrostatic force of the comb electrode creates the x-directional movement thus initial state is converted to the intermediate off-state. The initial off-state of the switch results in isolations of -31 dB, -24 dB and reflections of -0.45 dB, -0.67 dB at 50 GHz and 110 GHz, respectively. It shows the isolation degradation when the contact part moves right over the signal line of CPW like an initial off-state of a conventional MEMS switch. The isolations and reflections are -31 dB, -24 dB and -0.50 dB, -1.31 dB at 50 GHz and 110 GHz, respectively at the intermediate off-state.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.4 no.1
• /
• pp.71-75
• /
• 1994

In this study, a thermoelastic stress index of (100) oriented single crystalline silicon wafer and a relationship between thermal stress and critical plastic deformation temperatures were simulated. The simulated results for the thermoelastic stress index indicated a maximum value on <110> direction and a minimum on <100>. Then, it could be predicted that silicon wafer is plastically deformable over 1000 K, based on the relationship between the thermal stress derived from the thermoelastic stress index and the critical plastic deformation temperature.

• Electrical & Electronic Materials
• /
• v.9 no.3
• /
• pp.291-297
• /
• 1996

The surface properties of AI(Si, Cu) alloy film after plasma etching using the chemistries of chlorinated and fluorinated gases with varying the etching time have been investigated using X-ray Photoelectron Spectroscopy. Impurities of C, Cl, F and O etc are observed on the etched AI(Si, Cu) films. After 95% etching, aluminum and silicon show metallic states and oxidized (partially chlorinated) states, copper shows Cu metallic states and Cu-Cl$_{x}$(x$_{x}$ (x$_{x}$ (1

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.895-898
• /
• 1999

We calculated Al-Absorption, Al-reflection, and Si-etching probabilities as a function of incident angle and energy using classical molecular dynamics (MD) simulation. Variations of the cases of Al-absorption rate and Al-reflection rate are less than that of Si-etching rate. In contrast with general prediction, our simulation results showed that channeling of the <110> direction occurred the most in the case of incident angle between 30degree and 40degree. We investigated that channeling of the <110> directions quite affect Al-absorption rate in silicon. Since Si-etching rate is high and Al-absorption rate by <110> channeling is high, we found that Al ionized physical vapor deposition (PVD) on Si(001) has a different characteristics with Al ionized PVD on A1(111).