• Current Photovoltaic Research
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• 제2권4호
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• pp.147-151
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• 2014

A boron doping process using a boron tri-bromide ($BBr_3$) as a boron source was applied to form a $p^+$ emitter layer on an n-type mono-crystalline CZ substrate. Nitrogen ($N_2$) gas as an additive of the diffusion process was varied in order to study the variations in sheet resistance and the uniformity of doped layer. The flow rate of $N_2$ gas flow was changed in the range 3 slm~10 slm. The sheet resistance uniformity however was found to be variable with the variation of the $N_2$ flow rate. The optimal flow rate for $N_2$ gas was found to be 4 slm, resulting in a sheet resistance value of $50{\Omega}/sq$ and having a uniformity of less than 10%. The process temperature was also varied in order to study its influence on the sheet resistance and minority carrier lifetimes. A higher lifetime value of $1727.72{\mu}s$ was achieved for the emitter having $51.74{\Omega}/sq$ sheet resistances. The thickness of the boron rich layer (BRL) was found to increase with the increase in the process temperature and a decrease in the sheet resistance was observed with the increase in the process temperature. Furthermore, a passivated emitter solar cell (PESC) type solar cell structure comprised of a boron doped emitter and phosphorus doped back surface field (BSF) having Ni/Cu contacts yielding 15.32% efficiency is fabricated.

• 대한전자공학회논문지
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• 제23권1호
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 추계학술대회 논문집 전기물성,응용부문
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• pp.165-167
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• 2001

Emitter injection efficiency of p+/n-buffer Junction with Gaussian impurity distribution is presented. This model takes into account the variation of the carrier lifetime with injection level which allows a unified interpretation of the injection efficiency for all injection level. The injected carrier density and injection efficiency of the anode are calculated as a function of the current density with the low level lifetime as a parameter for different thicknesses of the anode. The analytical results agree well with simulation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.38-38
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• 2009

Wafer thickness of crystalline silicon is an important factor which decides a price of solar cell. PC1D was used to fix a condition that is required to get a high efficiency in a crystalline silicon solar cell using thin wafer($150{\mu}m$). In this simulation, base resistivity and emitter doping concentration were used as variables. As a result of the simulation, $V_{oc}$=0.6338(V), $I_{sc}$=5.565(A), $P_{max}$=2.674(W), FF=0.76 and efficiency 17.516(%) were obtained when emitter doping concentration is $5{\times}10^{20}cm^{-3}$, depth factor is 0.04 and sheet resistance is $79.76{\Omega}/square$.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권8호
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• pp.409-413
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• 2001

In the electron-gun of CRT, the Mo-tip FEA was employed as cold cathode in order to replace the conventional thermal cathode. The Mo-tip FEA was designed and fabricated according to CRT specification and mounted on the electron-gun. It was known that fabricated cold cathode electron-gun showed better performance in terms of maximum emission current and switch-on time when compared with the ones of thermal cathode electron-gun, but some geometrical structures in the inside of electron-gun must be changed to reduce the gate leakage current. Finally, the potential applicability was guaranteed by means of operating the 19 inch-sized LG-color CRT using the fabricated cold cathode electron-gun.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.270-273
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• 2006

In this study, ink-jet technology is applied to the emitter fabrication for surface-conduction electron-emitter display (SED). The general emiiter material of SED, palladium oxide (PdO), is prepared by calcination the mixture of solvent and precursors of platinum chlorine and platinum nitrate. With controlling the precursors and solvents, the PdO is formed below $400^{\circ}C$ which is required for SED process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.603-603
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• 2012

최근에 전면 emitter의 doping profile이 다른 selective emitter solar cell은 실제 제작시단파장 영역에서 많은 gain을 얻을 수 없어 LBC 구조의 태양전지에 관한 연구가 많이 진행되고 있다. 본 연구는 TCAD simulation을 이용하여 후면에 형성되는 locally doped BSF(p++) region의 doping profile의 변화에 따른 태양전지 특성에 관한 연구이다. Al으로 형성되는 local back contact의 doping depth 및 surface concentration에 따른 전기적, 광학적 분석을 통해 주도적인 인자를 분석하고 최적화하였다. 특히 doping depth에 따른 변화보다는 surface concentration의 변화에 따른 특성변화가 주도적으로 나타났다.

• ETRI Journal
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• 제28권3호
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• pp.386-388
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• 2006

Monolithic SiGe heterojunction bipolar transistor (HBT) variable gain amplifiers (VGAs) with a feedforward configuration have been newly developed for 5 GHz applications. Two types of the feedforward VGAs have been made: one using a coupled-emitter resistor and the other using an HBT-based current source. At 5.2 GHz, both of the VGAs achieve a dynamic gain-control range of 23 dB with a control-voltage range from 0.4 to 2.6 V. The gain-tuning sensitivity is 90 mV/dB. At $V_{CTRL}$= 2.4 V, the 1 dB compression output power, $P_{1-dB}$, and dc bias current are 0 dBm and 59 mA in a VGA with an emitter resistor and -1.8 dBm and 71mA in a VGA with a constant current source, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.235-238
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• 2007

eMagin's unique OLED-on-silicon microdisplay technology is unique and is based on small molecule white OLED with color filters using a top emitter structure. This paper will present results of recent improvements in the technology including improved lifetimes and uniformity and will feature an SVGA resolution full color microdisplay that is 0.44 inches diagonal.

• 대한전자공학회논문지
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• 제21권2호
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• pp.71-82
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• 1984

2차원 n-p-n 바이폴라 트랜지스터의 수치해석을 위한 프로그램(BIPOLE)을 개발하였다. 이 프로그램은 SRH와 Auger 재결합 기구들과 불순물 농도와 전계강도에 대한 운송자 이동도의 의존성과 밴드 갭 축소 효과들을 포함하고 있다. Poisson 방정식에는 Newton법을 또 정공과 전자의 연속 방정식에는 발산이론을 이용하여 여러가지 물리적인 제한없이 기본 반도체 방정식들에 대한 유한차분 공식들을 만들었다. 선형화된 방정식들의 계수 행렬은 희소 대칭 M 행렬이었는데 그 해를 구하기 위해 ICCG법과 Gummel의 알고리즘을 적용하였다. 이 프로그램 BIPOLE를 n-p-n 트랜지스터의 여러가지 정상 상태 문제에 적용시켰다. 그 응용의 보기로서 공통 에미터 전류이득의 변화, 에미터 용량에 대한 확산용량이 미치는 영향과 입출력 특성곡선들을 계산해 보았다. 전위 분포와 전자와 정공 농도분포와 같은 계산 결과를 3차원 컴퓨터 그래픽으로 도시하였다. 이 프로그램은 장차 2차원 트랜지스터의 교류 및 왜곡 현상의 수치해석의 기초로 이용될 것이며, 이 프로그램에 관심있는 모든 분들께 공급될 것이다.