• 한국재료학회지
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• 제1권4호
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• pp.229-235
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• 1991

$Ta_2O_5$ 박막은 실리콘산화막, 실리콘질화막 박막에 비해 유전율은 높으나 누설전류밀도가 높고, 절연파괴강도가 낮아 DRAM의 커패시터용 재료로서 실용화가 되지 못하고 있다. 본 연구에서는 LPCVD법으로 형성시킨 $300{\AA}$ 두께의 $Ta_2O_5$ 유전체박막에 대해 후속열처리 또는 전극재료를 변화시켜 열악한 전기적 특성의 원인을 규명하고자 하였다. 그 결과 다결정 실리콘 전극의 경우 성막상태의 $Ta_2O_5$ 박막은 전극에 의한 환원반응에 의해 전기적 특성이 열화됨을 알 수 있었고, 이를 TiN 전극의 사용으로 억제시킬 수 있었다. 다결정 실리콘 전극의 경우 성막상태의 $Ta_2O_5$ 유전체는 누설정류밀도가 $10^{-1}A/cm^2$, 절연파괴강도가 1.5MV/cm 정도였으며, $800^{\circ}C$에서 $O_2$열처리를 하면 전기적 특성은 개선되나, 유전율이 낮아진다 TiN 전극을 채용할 경우 누설전류밀도 $10^{-6}~10^{-7}A/cm^2$, 절연파괴강도 7~12MV/cm 로 ONO(Oxide-Nitride-Oxide) 박막과 비슷한 $Ta_2O_5$ 고유전막을 얻을 수 있었다.

• 한국세라믹학회지
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• 제42권2호
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• pp.104-109
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• 2005

PbO 완충층의 역할을 확인하기 위해, r.f. magnetron sputtering법을 이용하여 p-type (100) Si 기판 위에 $Pt/Pb_{1.1}Zr_{0.53}Ti_{0.47}O_{3}$와 PbO target으로 Pt/PZT/PbO/Si의 MFIS 구조를 제조하였다. MFIS 구조에 완충층으로 PbO를 삽입함으로써 PZT 박막의 결정성이 크게 향상되었고, 박막의 공정온도도 상당히 낮출 수 있었다. 그리고 XPS depth profile 분석 결과, PbO 증착시 기판온도가 PbO와 Si의 계면에서 Pb의 확산에 미치는 영향을 확인하였다. PbO 완충층을 삽입한 MFIS는 높은 메모리 윈도우와 낮은 누설전류 밀도를 가지는 추수한 전기적 특성을 나타내었다. 특히, 기판온도 $300^{\circ}C$에서 증착된 PbO를 삽입한 Pt/PZT(200nm, $400^{\circ}C)PbO(80nm)/Si$는 9V의 인가전압에서 2.OV의 가장 높은 메모리 윈도우 값을 나타내었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1992년도 제3회 학술발표회 논문개요집
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• pp.89-90
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• 1992

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권4호
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.188.2-188.2
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• 2015

The presence of the conduction interface in epitaxial $LaAlO_3/SrTiO_3$ thin films has opened up challenging applications which can be expanded to next-generation nano-electronics. The metallic conduction path is associated with two adjacent insulating materials. Such device structure is applicable to frequency-dependent impedance spectroscopy. Impedance spectroscopy allows for simultaneous measurement of resistivity and dielectric constants, systematic identification of the underlying electrical origins, and the estimation of the electrical homogeneity in the corresponding electrical origins. Such unique capability is combined with the intentional control on the interface composition composed of $SrTiO_3$ and $CaTiO_3$, which can be denoted by $SrxCa1-_xTiO_3$. The underlying $Sr_xCa1-_xTiO_3$ interface was deposited using pulsed-laser deposition, followed by the epitaxial $LaAlO_3$ thin films. The platinum electrodes were constructed using metal shadow masks, in order to accommodate 2-point electrode configuration. Impedance spectroscopy was performed as the function of the relative ratio of Sr to Ca. The respective impedance spectra were analyzed in terms of the equivalent circuit models. Furthermore, the impedance spectra were monitored as a function of temperature. The ac-based characterization in the 2-dimensional conduction path supplements the dc-based electrical analysis. The artificial manipulation of the interface composition will be discussed towards the electrical application of 2-dimensional materials to the semiconductor devices in replacement for the current Si-based devices.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 1997년도 제26회 추계학술대회
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• pp.183-190
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• 1997

The wear behaviors of $Al_2O_3-40%TiO_2$ deposited on casting aluminum alloy(ASTM A356) by plasma spray against SiC ball have been investigated experimentally. Friction and wear tests are carried out at room temperature. The friction coefficient of $Al_2O_3-40%TiO_2$ coating is lower than that of pure $Al_2O_3$ coating(APS). It is found that low friction correspond to low wear and high friction to high wear in the experimental result. The thickness of $Al_2O_3-40%TiO_2$ coatings indicated the existence of the optimal coating thickness. It is found that a voids and porosities of coating surface result in the crack generated. As the tensile stresses in coating increased with the increased friction coefficient. The columnar grain of coating will be fractured to achieve the critical stress. It is found that the cohesive of splats and the porosity of surface play a role in wear characteristics. It is suggested that the mismatch of thermal expansion of substrate and coating play an important role in wear performance. Tensile and compressire under thermo-mechanical stress may be occurred by the mismatch between thermal expansion of substrate and coating. This crack propagation above interface is observed in SEM.

• Tribology and Lubricants
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• 제15권1호
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• pp.39-45
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• 1999

The wear behavior of $Al_2$O$_3$-40%TiO$_2$deposited on casted aluminum alloy (ASTM A356) by APS (Air Plasma Spray) against SiC ball has been investigated in this work. Wear tests were carried out at room temperature. The friction coefficient of $Al_2$O$_3$-40%TiO$_2$coating is lower than that of pure $Al_2$O$_3$coating(APS). $Al_2$O$_3$-40%TiO$_2$coating indicated the existence of the optimal coating thickness. It is found that voids and pores of coating surface resulted in the generation of cracks, and the cohesive of splats and the porosity of surface play a role in wear characteristics. It is suggested that the mismatch of thermal expansion of substrate and coating play an important role in wear performance. Tension and compression under thermo-mechanical stress may be occurred by the mismatch between thermal expansion of substrate and coating. The crack propagation above interface is observed in SEM.

• 한국재료학회지
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• 제9권11호
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• pp.1129-1136
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• 1999

TEMAT precursor를 사용하여 다양한 증착 조건으로 ICP-CVD 방법으로 Si(100) 기판 위에 TiN 박막을 형성하였다. 형성된 TiN 박막의 결정상, 미세구조, 그리고 전기적 특성은 XRD, XPS, HRTEM, 그리고 전기적 측정으로 특성을 조사하였다. BI 구조를 갖는 다결정 TiN 박막은 기판의 온도가 $200^{\circ}C$ 이상의 온도에서 형성되었다. TiN(111) 박막은 기판의 온도가 $300^{\circ}C$에서 TEMAT, $\textrm{N}_{2}$, 그리고 Ar 가스의 유량이 10, 5, 그리고 5sccm으로 반응로에 주입할 때 형성되었다. TiN/Si(100) 계면은 TiN과 $\textrm{SiO}_2$사이에 계면반응이 없었으며 평탄하였다. 기판의 온도가 $500^{\circ}C$에서 형성된 TiN 박막의 비저항, carrier 농도와 이동도는 21 $\mu\Omega$cm, 9.5$\times\textrm{10}^{18}\textrm{cm}^{-3}$와 $462.6\textrm{cm}^{2}$/Vs으로 주어졌다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 춘계학술대회 논문집
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• pp.217-221
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• 1997

We have investigated the ferroelectric properties of multi-layered SrBi$_2$Ta$_2$$O_{9}$Pb(Zr,Ti)O$_3$, SBT/PZT, thin film capacitors. Specimens were prepared onto Pt-coated Si wafer by sol-gel method. Ferroelectric properties of these finns could be obtained only for thin SBT layers below 50nm in thickness. The values of dielectric constant and remnant polarization depend mainly on the thickness of SBT layer, which arises from the paraelectric interface layer between SBT and PZT due to the thermal diffusion of Pb. The value of remnant poarization of PZT/SBT is greater than that of SBT, and the plarization fatigue behaviors of PZT/SBT/Pt capacitors are somewhat improved as compared with those of PZT/Pt.t.

• 한국표면공학회지
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• 제36권1호
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• pp.14-21
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• 2003

Thin films of ZrO$_2$ and TiO$_2$ were deposited on Si(100) substrates using RF magnetron sputtering technique. To study an influence of the sputtering parameters, systematic experiments were carried out in this work. XRD data show that the $ZrO_2$ films were mainly grown in the [111] orientation at the annealing temperature between 800 and $1000^{\circ}C$ while the crystal growth direction was changed to be [012] at above $1000^{\circ}C$. FT-IR spectra show that the oxygen stretching peaks become strong due to $SiO_2$ layer formation between film layers and silicon surface after annealing, and proved that a diffusion caused by either oxygen atoms of $ZrO_2$ layers or air into the interface during annealing. Different crystal growth directions were observed with the various deposition parameters such as annealing temperature, RF power magnitude, and added $O_2$ amounts. The growth rate of $TiO_2$ thin films was increased with RF power magnitude up to 150 watt, and was then decreased due to a sputtering effect. The maximum growth rate observed at 150 watt was 1500 nm/hr. Highly oriented, crack-free, stoichiometric polycrystalline $TiO_2$<110> thin film with Rutile phase was obtained after annealing at $1000^{\circ}C$ for 1 hour.